The document summarizes key aspects of CPU and processor design, including: 1) It describes the stages of a MIPS pipeline, including instruction fetch, decode, execute, memory access, and write back. 2) It discusses hazards like structure hazards from conflicting resources, data hazards from instructions depending on previous results, and control hazards from branches. 3) Pipelining is introduced to improve performance by overlapping instruction execution, but it requires techniques like forwarding to address hazards between stages.

1. Chapter 4 The Processor [Adapted from Computer Organization and Design, 4 th Edition , Patterson & Hennessy, © 2008, MK] [Also adapted from lecture slide by Mary Jane Irwin, www.cse.psu.edu/~mji ]

4. CPU Overview Chapter 4 — The Processor — branch store load immediate

6. Control Chapter 4 — The Processor — (beq)

13. Instruction Fetch Chapter 4 — The Processor — 32-bit register Increment by 4 for next instruction

17. Branch Instructions Chapter 4 — The Processor — Just re-routes wires Sign-bit wire replicated Will be using it only to implement the equal test of branches

19. R-Type/Load/Store Datapath Chapter 4 — The Processor —

20. Full Datapath Chapter 4 — The Processor —

24. Datapath With Control Chapter 4 — The Processor —

25. R-Type Instruction Chapter 4 — The Processor —

26. Load Instruction Chapter 4 — The Processor —

27. Branch-on-Equal Instruction Chapter 4 — The Processor —

29. Datapath With Jumps Added Chapter 4 — The Processor —

34. Pipeline Performance Chapter 4 — The Processor — Single-cycle (T c = 800ps) Pipelined (T c = 200ps)

46. MIPS with Predict Not Taken Chapter 4 — The Processor — Prediction correct Prediction incorrect