Lecture 14 Caching And Tlbs

Caching and TLBs Andy Wang Operating Systems COP 4610 / CGS 5765

Caching ,[object Object],[object Object],[object Object]

Caching in Memory Hierarchy ,[object Object],[object Object],$0.001/MB < 200 GB 5-50 msec Disk Secondary memory $0.1/MB < 4GB 1-4 clock cycles Main memory <10 MB 1-2 clock cycles Cache On chip ~500 bytes 1 clock cycle Registers Primary memory Cost Size Access Time

Caching in Memory Hierarchy ,[object Object],[object Object],[object Object],[object Object],[object Object]

Locality in Access Patterns ,[object Object],[object Object],[object Object],[object Object]

Caching ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Generic Issues in Caching ,[object Object],[object Object],[object Object],[object Object],[object Object]

Effective Access Time ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Implications ,[object Object],[object Object],[object Object]

Reasons for Cache Misses ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Reasons for Cache Misses ,[object Object],[object Object],[object Object],[object Object]

Design Issues of Caching ,[object Object],[object Object],[object Object]

Caching Applied to Address Translation ,[object Object],[object Object],[object Object],[object Object],[object Object]

Caching Applied to Address Translation Virtual addresses Physical addresses Data reads or writes (untranslated) TLB Translation table In TLB

Example of the TLB Content Valid, rw 4 0 Invalid - - Valid, rw 1 2 Control bits Physical page number (PPN) Virtual page number (VPN)

TLB Lookups ,[object Object],[object Object],[object Object]

Direct Mapping ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Direct Mapping ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

TLB Lookups ,[object Object],[object Object],[object Object],[object Object]

Two-Way Associative Cache VPN VPN PPN VPN PPN VPN PPN VPN PPN VPN PPN VPN PPN hash = =

Two-Way Associative Cache VPN If miss, translate and replace one of the entries VPN PPN VPN PPN VPN PPN VPN PPN VPN PPN VPN PPN hash = =

Fully Associative Cache VPN VPN PPN VPN PPN VPN PPN hash = = =

Fully Associative Cache VPN VPN PPN VPN PPN VPN PPN If miss, translate and replace one of the entries hash = = =

Replacement of TLB Entries ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Replacement of TLB Entries ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Consistency Between TLB and Page Tables ,[object Object],[object Object],[object Object],[object Object],[object Object]

Relationship Between TLB and HW Memory Caches ,[object Object],[object Object],[object Object]

Relationship Between TLB and HW Memory Caches Data reads or writes (untranslated) VA data VA data Virtually addressed cache TLB PA data PA data Physically addressed cache PA data PA data PA data PA data Translation tables

Two Ways to Commit Data Changes ,[object Object],[object Object],[object Object],[object Object],[object Object]

Lecture 14 Caching And Tlbs

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