2. Terminology
Direct cache access
• Technology such that CPU can hit cache data of IO device on demand to
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avoid memory access
DCA
• Adopted since Xeon 5100 (Woodcrest)
• As a part of Intel IOAT
• OS/driver intervention required
PCIe TLP Processing Hints (TPH)
• PCI-SIG: PCI Express 2.1 Protocol Extensions
DDIO
• Adopted since Xeon E5 (SandyBridge)
• Likely to be a subset of PCIe TPH
• No OS/driver intervention required
3. DCA
Hardware Prefetch on DMA Write
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• Memory access cannot be avoided
• Need to avoid cache eviction before CPU uses
DCA flag := CPUID(EAX:1):ECX[18]
• Require driver’s intervention
TLP format for DCA
82599 datasheet: Fig.7.29
82599 datasheet: Fig.7.30 Available for multiple sockets
4. PCIe TLP Processing Hint (TPH)
“TPH is a performance feature that allows CPU to prefetch or keep
certain PCIe writeback data in LLC for quick core consumption.”
Steering Tag (ST) field: Identify target resources
• Three modes to derive ST value
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• No ST Mode
• Interrupt Vector Mode
• Device Specific Mode
10. Differences of DDIO from DCA
DDIO based on PCIe specification
• Not certain the usage of ST on DDIO from the public information
DDIO accelerate only for local socket, while DCA does not matter
• I don’t think that DCA contributed the performance for remote sockets
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