An introduction to the basics of DDR3

1. Jishnu Rajeev

2.  History
 Comparison
 DDR3
 Improvements
◦ Signaling
◦ Power
◦ Pin Out
◦ ODT
◦ Fly – By –Topology
◦ READ/WRITE Leveling
 Power Up
 Routing Guidelines

3.  DDR RAM was first introduced to allow data transfers on each edge of
the memory clock
 DDR technology has been developed because the actual DRAM chips
can‟t keep up with the data rates required by modern processors
 The DDR memory modules have a
64-bit interface so data is
transferred at 64 times the
transfer rate

4.  DDR3 is a member of the
SDRAM family of technologies
(DDR/ DDR2/ DDR3)
 DDR3 SDRAM - double-data-
rate three synchronous dynamic
random access memory
 DDR3 is a RAM interface
technology used for high
bandwidth

5. Items DDR3 SDRAM DDR2 SDRAM DDR SDRAM
Clock frequency 400/533/667/800 MHz 200/266/333/400 MHz 100/133/166/200 MHz
Transfer data rate 800/1066/1333/1600 Mbps 400/533/667/800 Mbps 200/266/333/400 Mbps
I/O width x4/x8/x16 x4/x8/x16 x4/x8/x16/x32
Prefetch bit width 8-bit 4-bit 2-bit
Clock input Differential clock Differential clock Differential clock
Burst length 8, 4 (Burst chop) 4, 8 2, 4, 8
Data strobe Differential data strobe Differential data strobe Single data strobe
Supply voltage 1.5V 1.8V 2.5V
Interface SSTL_15 SSTL_18 SSTL_2
CAS latency (CL) 5, 6, 7, 8, 9, 10 clock 3, 4, 5 clock 2, 2.5, 3 clock
On die termination
(ODT) Supported Supported Unsupported
Component package FBGA FBGA TSOP(II) / FBGA / LQFP

6.  Lower signaling standard
 Reduced power
 x8 Prefetch
 Dynamic ODT for improved Write signaling
 Fly-by architecture
 Read/Write Leveling
 Driver calibration
 Device Reset
 DIMM address mirroring
 Improved device pin out

8.  The following classes are defined by standard JESD8-6 from JEDEC:
◦ Class I (un-terminated/symmetrically parallel terminated)
◦ Class II (series terminated)
◦ Class III (asymmetrically parallel terminated)
◦ Class IV (asymmetrically double parallel terminated)
 SSTL buses –are less susceptible to
◦ overshoot
◦ undershoot
◦ ringing effects

9.  Supply voltage reduced from 1.8V to 1.5V
◦ 30% power reduction (Micron claim)
◦ 25% is JEDEC‟s official claim
(Compared to DDR2 at same frequency bin)
 Lower I/O buffer power
 34 ohm driver vs. 18 ohm driver at memory device
 Improved bandwidth per Watt

11. On – Die - Termination Termination Off Die

12.  Nominal ODT
◦ ODT (NOM) is the base termination resistance for each applicable ball, it is
enabled or disabled via MR1
 Dynamic ODT
◦ the termination strength of the DDR3 SDRAM can be changed without issuing
an MRS command, essentially changing the ODT termination on the fly
(RTT_NOM to RTT_WR during a a WRITE burst )
 Synchronous ODT Mode
◦ The DRAM‟s internal ODT signal is delayed a number of clock cycles defined
by the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2
and ODTL off = CWL + AL - 2.
 Asynchronous ODT Mode
◦ In asynchronous ODT mode, ODT controls RTT by analog time

16.  Allows for controller to determine the time delay for data command
to data output of each DRAM (byte lane)Enables controller to capture
data for each byte lane
◦ Write Leveling manages the DQS/DQ on write data
◦ Read Leveling manages the DQS/DQ on read data

18.  First the memory controller puts the DDR3 memory
devices into the read leveling mode by writing to the MR3
register MPR bit
 Causes output of a stream of “0101…”with a regular
memory read command(read training sequence)
 the memory controller will adjust the internal DQS delay
mechanisms on the read data path to create a proper
window of the best capture window for the DQ using DQS
 Once these internal compensations are created for each
DQS, the values will be stored for future usage
 MR3 is set back to normal DDR3 operational mode.

19.  Burst Length control (BC4/8 on the fly)
◦ 8-bit pre-fetch is standard for DDR3 memories
◦ Thus, burst length of 8 is default
 DDR3‟s also support „pseudo BL4‟using burst chip

20.  Improved system stability
◦ Eliminates unknown startup states
 Known initialization and recovery state
◦ Cold boot reset
◦ Warm boot reset
◦ Removes controller burden to ensure no illegal commands

21.  2X the bandwidth of DDR2
◦ Component per pin800 MT/s to 1600 MT/s
◦ Bus bandwidth6400 MT/s to 12,800 MT/s
 8 banks vs. 4 banks
◦ More open banks for back to back access
◦ Hide turnaround time
◦ Hide tRP

22.  Improved power delivery
◦ More power and ground balls
 Improved signal quality
◦ Better power & ground
distribution
◦ And better signal referencing
 Fully populated ball grid
◦ Stronger reliability
◦ Improved pin placement
 Less pin skew
◦ Tighter timing leaving chip

23.  Address inputs A[0:14]: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the
memory array in the respective bank.
 Bank address inputs BA[2:0] : define the bank to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied.
 Clock CK ,CK# : are differential clock inputs. All control and address
input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#.
 Clock enable: CKE enables (registered HIGH) and disables(registered
LOW) internal circuitry and clocks on the DRAM

24.  Chip select CS# : enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH
 Input data mask DM: is an input mask signal for write data.
 Command inputs RAS#, CAS#, and WE# : (along with CS#) define the
command being entered and are referenced to VREFCA.
 Data strobe DQS, DQS#: Output with read data. Edge-aligned with read
data. Input with write data. Center-aligned to write data

25.  Introduction of an asynchronous RESET# pin
◦ Prevent Illegal commands and/or unwanted states
 Cold reset
 Warm reset
◦ Known initialization
 Resets all state information
 No power-down required
 Destructive to data contents
 ZQ Calibration Pin
◦ The RZQ resistor is connected between the DDR3 memory and
ground
◦ Value = 240 Ohm +/-1%
◦ Permits driver and ODT calibration over process, voltage, and
temperatures

27.  DDR3 memories have two power pins defined.
◦ Same voltage level of 1.5V nominal
◦ Separate pins help reduce power supply noise/interruption
 VDD –Core Power
 VDDQ –IO Power
◦ Therefore, there will be 2 different cases:
 Case 1 –two separate sources
 Case 2 –Single voltage source for both rails

28.  The following should be applied whether a single voltage source or a
separate voltage sources are used:
◦ Apply Power: RESET# - to be maintained below 0.2V X VDD (min
200us) and all other inputs may be undefined
◦ The voltage ramp time between 300mV to VDD min must be no
greater than 200ms
 VDD > VDDQ, VDD-VDDQ < 0.3V
 The voltage levels on all other pins should not exceed VDD/VDDQ or
be below VSS/VSSQ

29.  Impedance
◦ All signal planes must be 50 , single-ended, ±10%.
◦ All signal planes must be 100 , differential ±10%.
◦ All unused via pads must be removed, because they cause unwanted
capacitance.
 Decoupling Parameter
◦ Use 0.1 F in 0402 size to minimize inductance.
◦ Make VTT voltage decoupling close to the DDR3 SDRAM components and
pull-up resistors.
◦ Connect decoupling caps between VTT and VDD using a 0.1 uF
cap for every other VTT pin.
◦ Use a 0.1F cap and 0.01F cap for every VDDQ pin.

30.  Power
◦ Route GND,1.5 V and 0.75 V as planes.
◦ Route VCCIO for memories in a single split plane with at least a 20-mil
(0.020 inches, or 0.508 mm) gap of separation.
◦ Route VTT as islands or 250-mil (6.35-mm) power traces.
◦ Route oscillators and PLL power as islands or 100-mil (2.54-mm) power
traces.
 General Routing
◦ Use 45° angles (not 90° corners).
◦ Disallow critical signals across split planes.
◦ Route over appropriate VCC and GND planes.
◦ Keep signal routing layers close to GND and power planes.
◦ Avoid routing memory signals closer than 0.025 inch
(0.635 mm) to memory clocks.

31.  Clock Routing
◦ Route clocks on inner layers with outer-layer run lengths held to under
500 mils (12.7 mm).The maximum length of the first SDRAM to the last
SDRAM must not be more than 5 inches (127 mm) or 0.69 tCK at 1.066 GHz
◦ Clocks should maintain a length-matching between clock pairs of ±5 ps
or approximately±25 mils (0.635 mm).
◦ Differential clocks should maintain a length-matching between positive (p)
and negative (n) signals of ±2 ps or approximately ±10 mils (0.254 mm),
routed in parallel.
◦ Space between different pairs should be at least two times the trace width
of the differential pair to minimize loss and maximize interconnect
density.

32.  Address and Command Routing
◦ Route address and command signals in a daisy chain topology from the
first SDRAM to the last SDRAM. The maximum length of the first SDRAM to
the last SDRAM must not be more than 5 inches (127 mm) or 0.69 tCK at
1.066 GHz.
◦ Do not route differential clock (CK) and clock enable (CKE) signals close to
address signals.
 External Memory Routing Rules
◦ Match in length all DQ, DQS, and DM signals within a given byte-lane
group with a maximum deviation of ±10 ps or approximately ± 50 mils
(± 1.27 mm).
◦ Ensure to route all DQ, DQS, and DM signals within a given
byte-lane group on the same layer

33.  Termination Rules
◦ Use an external parallel termination of 40 Ohm to VTT at the end of the
fly-by daisy chain topology on the addresses and commands.
◦ Keep the length of the traces to the termination to within 0.5 inch (14
mm).
◦ Use resistors with tolerances of 1 to 2%.

35.  Expected to run at 1.2 V or less
 At clock speeds up to 4266 MT/s
 Up to 40% Energy Efficient .
 Discards dual and triple channel
approaches in favor of point-to-point
where each channel in the memory
controller is connected to a single
module
 The first DDR4 memory module was
manufactured by Samsung and
announced in January 2011.