This document presents a novel approach to emulate power islands in FPGA platforms to enable earlier validation of low power features. It proposes corrupting logic in power-gated domains by connecting power gating enables to asynchronous set/clear signals on flip-flops. This approach more realistically mimics silicon behavior during power-off and can find issues like incorrect power sequencing bugs. The methodology was implemented using a custom EDF library and randomization to corrupt a parameterized percentage of logic. Challenges around FPGA architecture and optimization were addressed. Results showed the approach introduced minimal overhead while enabling important power management validation earlier in the design flow.

1. SNUG 2016 1
A novel approach to Power Island Emulation in
FPGA Platforms
A Shift-Left Methodology
Jaseel Abdulla
Madhusudan Chidambaram
Intel Corporation
July 13, 2016
Bengaluru

2. SNUG 2016 2
Agenda
Motivation
Introduction
Problem Statement
Potential Silicon Issues
Proposed Solution
Challenges
Results and Summary

3. SNUG 2016 3
Motivation
Shift left SOC low power validation using FPGA’s
Time to Market
Design Complexity
Power Gating Features
Time Cost
FPGA Prototype
Power Gate Flows
Android/Linux/Windows
Buggy
Silicon

4. SNUG 2016 4
Introduction
• SoC have multiple power rails and different combinations for each sub system.
• Complex PST requirement.
• Retention for flop/memory
• Low Drop Out Regulator or LDOs
• Fully Integrated Voltage Regulators or FIVRs
• Dynamic Clock gating
• Complex PMIC flows
• Low Cycle PowerUp/Down sequence requirement.
Power Domain complexity in todays SoCs

5. SNUG 2016 5
Introduction
Why FPGAs
• Only FPGA Platforms can work with real world interfaces.
• Enable faster FW/SW driver development.
• Less turn around time for Regression and stress testing
• Complex low power use case testing involving multiple IPs
• First hand validation platform for IP HW teams.
• Boot flow bring up much early before actual Silicon.
• Develop System level test content
• Cost effective compared to ‘BIG BOX’ Emulation platforms

6. SNUG 2016 6
What is missing today ?
Power Island Emulation
• Over the years, power management has become one of the most challenging and critical
piece in SoC design and FW development.
• Power aware emulation enabling Operating System Power Management [OSPM] and FW
has been a major challenge in ASIC verification.
• FPGA prototype is in critical path for OS testing before Tape Out but no FPGAs available in
market supporting power Islands.
• Puts a hard restriction in validating OSPM or Low Power BIOS/Firmware driver sequence in
FPGA platforms.
• Ad-hoc methods like accelerators are not ideal as it lags real world IO connectivity, slow
speed and very high cost.
1.2 V
1.0 V 0.9 V
OFF
1.2 V
1.0 V OFF
Sub system
power down
SOC
validation

7. SNUG 2016 7
Problem statement
Mimicking real silicon
• As FPGA by design does not support multiple power regions, how do we emulate
multiple power islands ?
blk0 blk1
blk2
ps0
ps1
ps2
Retentions
iso
PM Ctrl
On-Off
• What happens to the logic in “blk1” when
the power rails gets shut-off.
• Simulation tools use corruption by using X
injection to reproduce rail shutdown and in
FPGAs we cant inject X.
• Now What ?
• We need a way to corrupt the logic when
power is shutdown for a domain.
• Need to mimic random behavior similar to
silicon.

8. SNUG 2016 8
Potential Issues in Silicon
Missed scenarios in buggy silicon !

9. SNUG 2016 9
Potential Silicon Issues
• Designs today have Auto Power gating, where power up/down sequencing are done by FSM
– Traditionally the power sequence is done by SW drivers/OSPM
– Sequencing bugs are difficult to debug in post-silicon
• Incorrect sequencing of power control signals can result in silicon issues (Isolation enable,
reset enable, power switch enable / clock enables).
– During power-up, if the isolation enable is released ahead of the power switch enable being released ,
un-initialized values will be propagated out of the design that is being powered up.
– If reset is asserted and released before releasing power enable (instead of after releasing the power
enable), the reset will not take into effect and flops would power up with random values.
Example 1: Incorrect Power Sequencing

10. SNUG 2016 10
Potential Silicon Issues
Example 2: Reset propagation Issues
• Flops with wrong reset control, or functional reset not
connected or not propagated because of masking logic in the
power island.
• IP Reset is asserted for every power up of the domain and
power on reset asserted once for every cold reset of SoC
• When the power island is powered back and functional reset
is reasserted, the flop will come back up with random values,
whereas the rest of the flops in the design will have correct
values, resulting in a failure.
Module A
Module B
Module C
Module E
Module F
Power on Reset : Asserted once
for every cold reset of SoC
Reset Override logic

11. SNUG 2016 11
• Many CDC Tools today don’t take UPF as input and analyze
path introduced by isolation logic.
• Pre-Si Verification uses UPF and do “X” injection but they
can’t catch CDC issues.
• However FPGA based emulation can bring out CDC issues.
• IP1 and IP2 are in the same clock domain, however IP2
could be power gated, hence there is output isolation logic.
– The isolation enable comes from a power management
controller which is in a different clock domain.
– If the IP2 by default parks the logic in “0” , there is no issue.
However if the IP2 value is parked to “1” , there is a CDC path
from clock domain C to Clock domain A
• Similarly for the case from IP4 to IP3
IP 1
IP 4
IP 2
IP 3
CLK_A
CLK_C
GATED DOMAIN
GATED DOMAIN
Potential Silicon Issues
Example 3: CDC on Isolation logic.
CLK_A
CLK_A
CLK_B
PM Ctrl
CLK_C

12. SNUG 2016 12
Potential Silicon Issues
Few more !!
• LDO powering the memory wrongly sequenced in the Flow.
• If an LDO powering a memory is accidentally or wrongly sequenced, the content of the
memory could be lost.
• Typically Pre-Si environment wouldn’t model LDO and Memory Power structures and
therefore these effects cannot be caught in simulation.
• Missing/incorrect polarity output isolation cell, this can result in functional issues when the
island is power gated.
• In order for Pre-Si simulations to catch these issues, all the inter connected power
domains need to be concurrently tested.
• Many a times due to simulation run times, concurrency testing is pushed to Big-Box or
FPGA

13. SNUG 2016 13
Approaching the solution
• In summary, the block under power gated condition should be non-functional or corrupt in a
random way, to propagate the errors.
• How do we achieve this? Can I apply reset to blocks when power gated. This got two issues.
– If we forget to apply reset in the actual sequence, it will get missed.
– This may not propagate some of the real silicon issues explained in the previous slides.
• Corrupt only the peripheral logic, which are isolated in the design. ( essentially all outputs and
inputs). This will not again propagate and bring out other examples shared in previous slides.
• Corrupt all the logic in the block when power-gated, including memories.
– This is our proposed solution.
– Challenge is to achieve this with minimal resource and timing impact to emulation.

14. SNUG 2016 14
Proposed Solution
LP Modelling

15. SNUG 2016 15
Basic Principle
How do I corrupt logic pessimistically?
• Power switches gets added post synthesis and these power switches are controlled by
enables.
• Use these power gating enable as an addition asynchronous set/clear signal.
• Flops having asynchronous clear, pgen is connected to asynchronous set and vice-versa.
• This is a fully pessimistic approach
• These pgen signal should have higher priority over functional existing asynchronous signal..
• This is needed to cover examples 1 and 2
d q
s
r
d q
s
r
pgen
d q
s
r
d q
s
r
Asynchronous reset flop conversion Asynchronous set flop conversion
pgen

16. SNUG 2016 16
Making this more realistic
Custom EDF library
• In real silicon the corruption would happen more
randomly and this is modelled by;
 Parameter passing for how much % of logic needs to be
corrupted
 Randomize the logic in different subsystems that will get
corrupted
• Streamlining the corruption flow.
 A custom edf library is created for mapping different
types of flops getting mapped to FPGAs named
‘CUSTOM_EDF”
D Flip-Flop with Asynchronous Clear
D Flip-Flop with Clock Enable

17. SNUG 2016 17
Methodology Flow
Normal Flow Vs PD corruption Flow
RTL+SDC UPF
Synthesis
Pre-Mapping + Mapping
PAR
Normal FPGA Implementation flow

18. SNUG 2016 18
Methodology Flow
Existing Flow Vs PD corruption Flow
RTL+SDC UPF
UPF Parser PD Info
reports
Pre-mapping
Netlist Editing to connect new pgen pin
to PD hierarchies
Mapping
netlist_edit.tcl
edf
edf
EDF Parser
custom_edif
library
Dump corrupted edf file
User input for PD and % flops
for corruption
Flops gets replaced by
“custom_edif” library cells
PGEN pin gets connected from
PD hier to custom cells
PAR
New FPGA Implementation flow
New
Existing

19. SNUG 2016 19
Retention Register Modeling
Save Restore sequence in retention
• Retention strategy in SOC relies on ”save” and “restore” sequence for data retention.
• Qualification for data corruption is decided by the sequencing. Any error in power down/up
sequencing should qualify for logic corruption.

20. SNUG 2016 20
Memory Modeling
LFSR pattern based corruption.
• An LFSR gets triggered when the memories are
power gated and random data gets written to
memories while power gated.
• Read Enables kept asserted during power gating
allowing corrupted values to propagate to
interfaces and detect if firewalls are not inserted
properly.
• LFSR seed value is changed to change data
corruption value between every runs.
• Faster clock gets connected to LFSR counters.
• Memory clock gets gated during Power Down,
hence used XMR reference system clock.
Memory
LFSR Counter
clk
addr
wr_data
wr_en
rd_en
LFSR_clock
vcc
pgen
bpwenb
Random load pattern
clk
addr
wr_data
wr_en
rd_en
enable lfsr

21. SNUG 2016 21
Challenges
Engineers are made to create solutions

22. SNUG 2016 22
FPGA architecture challenge
Xilinx V7 Architecture.
Scope for optmization

23. SNUG 2016 23
Implementation Challenge
Latch optimization.
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FFLATCH
FF
LATCH
FF
FF
FF
FF
FF
LATCH
FF
FF
FF
FF
FF
FF
Reset Domain 1 Reset Domain 2 Reset Domain 1 Reset Domain 2
syn_insert_buffer

24. SNUG 2016 24
Results

25. SNUG 2016 25
Results
IP Changes with different corruption levels
LUTs
Flops
Latches
0
20000
40000
60000
80000
100000
120000
140000
0% 20% 25% 50% 50 %
Optmised
LUTs Flops Latches
LUTs
Flops
Latches
0
5000
10000
15000
20000
25000
30000
0% 20% 25% 50% 50 %
Optmised
LUTs Flops Latches
IP - 1 IP - 2

26. SNUG 2016 26
Results
Frequency changes
0
10
20
30
40
50
60
70
80
90
100
0% 20% 25% 50%
FREQUENCY
CORRUPTION LEVEL
uart fast clk uart slow clk usb core clk usb phy clk

27. SNUG 2016 27
Summary
• Help find power sequence bugs much earlier in design flow.
• One time effort to put the methodology in place and reusable in any projects and any target
FPGAs.
• Help OSPM full fledge validation, application/fw development much before actual silicon.
• Pull the overall schedule by 3-4 weeks.
• HW SW Co validation and Performance Check.
• Save $ for the company; avoid re-spins and stepping's.
Conclusion
Future work
• Work with Synopsys to get this feature implemented in FPGA tools.
• Emulating power rails, regulators and PMIC

28. SNUG 2016 28
Thank You