2. Product
Development Substrate
Handling
Fab Mftg
DAETEC
Support
Analytical
Testing
Bridging Your Success
Process
Toll Development
Intellectual
Property Support
DAETEC
Diversified
Applica@ons
Engineering
Technologies
2
3. Daetec
Business
Model
• What
We
Do:
Product
development
and
consul>ng
• How
We
Do
it:
Formulate
commercially
available
ingredients
&
apply
to
a
process
• Primary
Experience:
Coa>ngs
&
cleaning
products
• Deliverables:
New
product
or
ancillary
• Clients:
Materials
&
equipment
suppliers,
end-‐
users
(manufacturing)
DAETEC
Diversified
Applica@ons
Engineering
Technologies
3
5. Concept
to
Commercializa>on
Daetec
Daetec
Daetec
Proof
of
Demo
Prototype
Concept
Client
Client
Daetec
Mass
Commercial
Technology
Produc@on
Scale-‐Up
Transfer
Timing,
Demo
–
Tech
Transfer
~6mos
DAETEC
Diversified
Applica@ons
Engineering
Technologies
5
6. Daetec
Working
Rela>onship
Suppor2ng
Market
Leaders
• The
staff
at
Daetec
have
developed
products,
patents,
wriUen
papers,
and
presented
work
with
a
wide
number
of
leaders
in
the
industry.
Our
work
spans
temporary
adhesives
used
in
3DIC
to
PR
and
residue
removal
processes.
DAETEC
Diversified
Applica@ons
Engineering
Technologies
6
7. What
is
3DP?
• 3DP
–
3D
Packaging
(Chip
Stacking)
• Process:
Thinning,
TSVs
for
connec>vity,
metal
for
heat
dissipa>on,
stacking
• Similar
or
mul>ple
types
of
chips
DAETEC
Diversified
Applica@ons
Engineering
Technologies
7
8. Thin
Wafer
support
Thin
Wafer
Thickness
Chem
&
Single
Backside
Handling
Min
(um)
Therm
Wafer
or
Processing
Resistant
Batch
Support
Tape
>50
No
Both
No
Vacuum
>50
No
Single
No
Chuck
Adhesive
<25
Yes
Both
Yes
Bonded
Carrier
Thinner
is
Must
be
Versa@lity
Must
do
BeXer
Resistant
Is
Best
Backside
Processing
DAETEC
Diversified
Applica@ons
Engineering
Technologies
8
9. Temporary
Spin-‐On
Adhesive
Coa@ng
and
Moun@ng
Model
Substrate
with
Coat
&
fix
on
substrate
So]/hard
bake
topography
Penetra@on
and
seng
Drive-‐off
vola@les,
planarize
Bonding
to
carrier
Adhesion
on
cooling
Substrate
Thinning
Planarized
substrate
surface
Maintain
pressure
Grind,
polish,
stress
relief
Carrier
wafer
is
mounted
to
the
wafer
to
be
thinned
and
used
to
“handle”
or
“support”
the
thinned
wafer
through
all
the
steps
of
backside
processing
DAETEC
Diversified
Applica@ons
Engineering
Technologies
9
10. Integra>ng
Thin
Wafers
&
Bumping
Through Hole
Contact Bond Pad
Device Build Completed
Wafer
Full size wafer
Solder Bump
Bumps
Complete
Thinned Wafer
Carrier or no- Thinning
&
Back-‐
carrier attached
Vias and Side
Processing
Using
metallization
Adhesive/Carrier
Flip-chip to
solder bump on
board lead
mount with Flip-‐chip
mounted
epoxy
To
board
DAETEC
Diversified
Applica@ons
Engineering
Technologies
10
11. Range of Coatings Available
• Solvent or water casting
• Thermoplastic or thermoset
• Evaporative (bake) or UV initiated cure
• Thermal resistance min. 200C; systems
at >500C for extended time are possible
• Many are moisture and/or chemical
resistant
• Transparency is possible
DAETEC
Diversified
Applica@ons
Engineering
Technologies
11
18. Simple and Rapid UV Curing
Low emission source UV LED Lamp
UV LED Designed Source
DAETEC
Diversified
Applica@ons
Engineering
Technologies
18
19. LED vs. Hg-Arc LED
Narrow
Emission
DAETEC
Diversified
Applica@ons
Engineering
Technologies
19
20. Low Outgas Product for CVD
Targets for successful CVD processing:
• Low permeability coating
• High Tg
• If amorphous, high softening/melting point
• Softening/melt pt is > process temp
• Design cure program as > process temp
DAETEC
Diversified
Applica@ons
Engineering
Technologies
20
21. Barrier Usage for Reduced Outgas
Gas Barrier
Properties
Assist with
formulating low
outgas coatings
DAETEC
Diversified
Applica@ons
Engineering
Technologies
21
22. Process Overlay
SP – softening point
50 100 CVD
150 200 250
Cure
Program
SP
De-‐Bond
50 100 150 200 250
Temperature
DAETEC
Diversified
Applica@ons
Engineering
Technologies
22
24. Low COO Development for Solar
• Solar manufacturer of <10um thick substrates
• Suggest to eliminate spin-coating adhesive
with a film lamination practice
• Use SEMI Std E35 for COO comparison of
the technologies; use a ratio between COO2
(new) and COO1 (current)
• Assumptions: similar yield, internal costs,
scrap, life, maintenance, etc.
• Tool costs, service, support, etc., identified as
a factor of material costs
DAETEC
Diversified
Applica@ons
Engineering
Technologies
24
25. COO for Technology Comparison
Adhesive
Liquid
Spin-Coat Process
Adhesive
Film lamination Process
DAETEC
Diversified
Applica@ons
Engineering
Technologies
25
26. COO Comparison of Technologies
COO
=
F$+R$+Y$
Costs
=
L×T×Y×U
Product
Item
Defini@on
F$
Fixed
Costs
COO2 Film Adhesive
R$
Recurring
Costs
COO1 = Liquid Adhesive
Y$
Yield
Cost
(scrap)
L
Equipment
Life
T
Throughput
Y
Composite
Yield
U
U@liza@on
DAETEC
Diversified
Applica@ons
Engineering
Technologies
26
27. COO Calculations
COO
2
F$2+R$2+0
L×T×Y×U
COO
1
=
L×33T2×Y×U
X
F$ +R$ +0
1 1
COO
(0.38R$ +R$
)
0
2 = 2
2
=
.038R$2 = 0.0027
COO
1
33(0.087R$ +R$
)
R$
1 1 1
The COO for integrating a film adhesive is 0.3% of
the COO for a liquid adhesive.
DAETEC
Diversified
Applica@ons
Engineering
Technologies
27
28. Daetec’s
Experience
Temporary
Adhesive
Development
Date Description Customer Chemistry Product
Pre-2000 Wafer dicing & Johansen Rosin/ AquaBond
cleans Technology oligomer 55 & 85
2000 First spin-on GCC – Rosin/ GenTak 230
adhesive Motorola urethane
2004 First spin-on high- GCC – Silicone GenTak 330
temp thermoset INTEL
2005 First spin-on high BSI Rubber BSI HT1010
temp, acid resist
2009 First spin & spray SUSS Acrylic SS1101
wafer molding composite
2011 First wafer TCTI Urethane Adh-U
lamination for solar
DAETEC
Diversified
Applica@ons
Engineering
Technologies
28
29. Daetec Issued Patents
Temporary Adhesives for Thin Substrates
• US Patent #6,869,894: Spin-on adhesive for temporary
wafer coating and mounting to support wafer thinning and
backside processing
• US Patent #7,098,152: Adhesive support method for wafer
coating, thinning, and backside processing
• US Patent #7,232,770: High temperature and chemical
resistant process for wafer thinning and backside processing
• US Patent #7,678,861: Thermal and chemical-resistant acid
protection coating material and spin-on thermoplastic
adhesive
• Two additional applications in 2009 (not-issued)
DAETEC
Diversified
Applica@ons
Engineering
Technologies
29
30. Daetec
for
Temporary
Adhesives
• Include
an
expert
on
your
team
• Low-‐cost
adhesives
are
available
• Increase
throughput
-‐
migrate
from
single-‐
wafer
to
batch
(from
6
wph
to
>100
wph)
• Process
tuning
to
your
process
• You
own
the
adhesive
and
process
• Conven>onal
comparison,
COO
is
<50%
and
<10%
depending
upon
usage
DAETEC
Diversified
Applica@ons
Engineering
Technologies
30
31. Contact for More Information
• DAETEC provides new product development,
consulting, and technical support to solve
manufacturing problems and introduce new
options of doing business.
• Diversified Applications Engineering
Technologies (DAETEC)
Camarillo, CA (USA) (805) 484-5546
jmoore@daetec.com; www.DAETEC.com
DAETEC
Diversified
Applica@ons
Engineering
Technologies
31