O que há de novo na plataforma x86 para High Performance por Jefferson de A Silva

O que há de novo na plataforma x86 para High Performance Jefferson de A Silva Systems Management & Product Specialist [email_address]

Por que sistemas de alta performance

A tendência tecnológica – Todo ano nós ficamos mais rápidos mais processadores Breakdown in Frequency scaling ,[object Object],[object Object],[object Object],[object Object],Intel CPU Trends (sources: Intel, Wikipedia, K. Olukotun) Pentium 386 Xeon Paxville Montecito

Aspectos de Planejamento de Capacidade em ambiente x86 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Aspectos de Planejamento de Capacidade em ambiente x86 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Aspectos de Planejamento de Capacidade em ambiente x86 Network Architecture – Standard NIC CPU CPU LAN Memory Chipset 1 2 3 4 ,[object Object],[object Object],[object Object],[object Object],LAN

Aspectos de Planejamento de Capacidade em ambiente x86 TCP/IP Offload - TOE ,[object Object],[object Object],[object Object],CPU CPU LAN Memory Chipset 1 2 3 1 2 TOE

Aspectos de Planejamento de Capacidade em ambiente x86 I/O Acceleration Technology – Intel (IOAT) CPU CPU LAN Memory Chipset 1 2 3 ,[object Object],[object Object],[object Object],4 LAN

Memory Controller Memory Bus 400 MHz Memory Controller Memory Bus 533 MHz 667 MHz Memory Controller Memory Bus Not representative of any particular system Diagram is intended to illustrate speed and DIMM count limitations Aspectos de Planejamento de Capacidade em ambiente x86 And We Still Have The Capacity vs. Speed Trade-off DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

FBDIMM Solves This Problem With Serial Memory Bus And On-DIMM Advanced Memory Buffer (AMB) Serial Address Bus Serial Data Bus Same DDR2 DRAM Technology Memory Controller

FBDIMM Serial Bus Add Latency Due to Hops Serial Address Bus Serial Data Bus Memory Controller Address Data

Additional Memory Channels = Greater Capacity And Greater Throughput Which Offsets Additional Latency Under Load DDR2 Memory Controller FBD Memory Controller Greater Memory Bandwidth Less Memory Bandwidth DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Measured DDR2 vs. FBD Memory Throughput 39% Increase 2.8x Increase 39% Increase 2.8x Increase

CPU Bottleneck Performance Fundamentals ,[object Object],[object Object],[object Object],Potential Processor Bottlenecks Core Intensive Bandwidth Intensive Latency Intensive

Xeon vs. Opteron Performance Fundamentals Dual Core System Design ,[object Object],[object Object],[object Object],Potential Processor Bottlenecks Core Intensive Bandwidth Intensive Latency Intensive Woodcrest,Clovertown and Tulsa Win By as much as 20+% X3 Xeon Wins Woodcrest and Opteron About the same Opteron Wins by as much As 2X

PCI Memory Bridge Memory Bridge Memory Bridge Xeon Coherency Protocol – CPU Snoop Request PCI PCI PCI IO Controller USB, IDE, SATA,etc Memory Bridge Memory Controller Cache Miss Read Data Snoop All Other Processor Caches

Xeon Coherency Protocol – CPU Snoop Response PCI Memory Bridge PCI PCI PCI IO Controller USB, IDE, SATA,etc Only Now Can Processor Operate on Data! Memory Bridge Memory Bridge Memory Bridge Memory Controller

Xeon Coherency Protocol – DMA Snoop Request PCI Memory Controller Memory Bridge Memory Bridge Memory Bridge Memory Bridge PCI PCI PCI IO Controller USB, IDE, SATA,etc DMA Read Data Snoop All Processor Caches

Xeon Coherency Protocol – DMA Snoop Response PCI Memory Controller Memory Bridge Memory Bridge Memory Bridge Memory Bridge PCI PCI PCI IO Controller USB, IDE, SATA,etc Only Now Can Memory Be Accessed! Snoop Responses Returned

AMD Architecture – Local Memory Access HyperTransport ™ PCI-X 100Mhz PCI-X 100Mhz HyperTransport 6.4GB/s coherent HyperTransport PCI-X 100Mhz HyperTransport PCI-X 133Mhz HyperTransport PCI-X 133Mhz AMD Opteron CPU 0 AMD Opteron CPU 1 AMD Opteron CPU 3 AMD Opteron CPU 2 PCI-X Bridge PCI-X Bridge PCI-X Bridge HyperTransport ™ HyperTransport ™ Processor Cache Miss – Local Read ,[object Object],HyperTransport 6.4GB/s coherent HyperTransport HyperTransport ™

AMD Architecture – Local Memory Access HyperTransport ™ PCI-X 100Mhz PCI-X 100Mhz HyperTransport 6.4GB/s coherent HyperTransport PCI-X 100Mhz HyperTransport HyperTransport PCI-X 133Mhz AMD Opteron CPU 0 AMD Opteron CPU 1 AMD Opteron CPU 3 AMD Opteron CPU 2 PCI-X Bridge PCI-X Bridge PCI-X Bridge HyperTransport ™ HyperTransport ™ HyperTransport 6.4GB/s coherent HyperTransport HyperTransport ™ Snoop CPU 1,3 Snoop CPU 2 Snoop CPU 3 Snoop Response From CPU1 Snoop Response From CPU2 Snoop Response From CPU3 Snoop Response From CPU3 ,[object Object],[object Object],[object Object],PCI-X 133Mhz

AMD Architecture – Local Memory Access HyperTransport ™ PCI-X 100Mhz PCI-X 100Mhz HyperTransport 6.4GB/s coherent HyperTransport PCI-X 100Mhz HyperTransport HyperTransport PCI-X 133Mhz AMD Opteron CPU 0 AMD Opteron CPU 1 AMD Opteron CPU 3 AMD Opteron CPU 2 PCI-X Bridge PCI-X Bridge PCI-X Bridge HyperTransport ™ HyperTransport ™ Only now can execution proceed! HyperTransport 6.4GB/s coherent HyperTransport HyperTransport ™ Read Complete And Usable PCI-X 133Mhz

Processor Futures ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Opteron Next Gen Processors Add Faster DDR2 Memory Opteron with DDR2 Memory Controller Opteron with DDR2 Memory Controller Rev E 266/333MHz DDR1 -> 400/533 MHz DDR2 Opteron with DDR2 Memory Controller Rev E 400MHz DDR1 -> 667 MHz DDR2 Rev E 400MHz DDR1 -> 800 MHz DDR2 DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Opteron Dual-Core Design Cache to Cache data sharing is done through crossbar switch. CPU0 1MB L2 Cache CPU1 System Request Interface Crossbar Switch Memory Controller HT0 HT1 HT2 AMD Opteron™ Architecture 1MB L2 Cache

AMD Opteron Quad-Core Design: Barcelona CPU1 Crossbar Switch Memory Controller HT0 HT1 HT2 AMD Opteron™ Architecture System Request Interface L3 Cache Quad Core Design: Adds L3 Cache CPU0 L2 Cache CPU1 L2 Cache CPU3 L2 Cache CPU2 L2 Cache

Xeon 5100 Series (Woodcrest) DP Architecture Source: Intel public data

Wide Dynamic Execution From: http://www.intel.com/technology/architecture/coremicro/#anchor2 ,[object Object],Net Burst Core Microarchitecture

Xeon vs. Core ™ Dual-Core Design Cache to cache data sharing is now done through shared cache Cache to cache data sharing was done through bus interface (slow) CPU0 2MB L2 Cache Intel Xeon Dual-Core Architecture CPU1 2MB L2 Cache Bus Interface ,[object Object],Intel Core™ Architecture CPU0 CPU1 4 MB Shared Cache Bus Interface

Intel Core ™ Quad-Core Design 4 MB Shared Cache Bus Interface Bus Interface 4 MB Shared Cache FSB ,[object Object],[object Object],[object Object],MCM to MCM data sharing is done through bus interface (slow) CPU2 CPU3 CPU0 CPU1

3x @ 34.1GB/s 10.6 GB/s 2x @ 42.6GB/s 21.3 GB/s 1.6x @10.4GB/s 6.4 GB/s ,[object Object],[object Object],[object Object],[object Object],to X4 – Architectural Improvements

2 Socket Product Positioning Today – AMD Dual core and Intel Quad core INTEL AMD Integer Processing HPC – core intensive BPC – core intensive Web-serving Java Database Collaboration Virtualization File and Print HPC – bandwidth intensive EDA Video Streaming Media encode/decode BPC – bandwidth intensive Large memory set workloads Memory Bandwidth/Capacity Core Processing Clovertown Next Gen - RevF Data mining SAP

2 Socket Product Positioning 3Q07 – AMD Quad core and Intel Quad core INTEL AMD Integer Processing HPC – core intensive BPC – core intensive Web-serving Java Database Collaboration Virtualization File and Print HPC – bandwidth intensive EDA Video Streaming Media encode/decode BPC – bandwidth intensive Large memory set workloads Memory Bandwidth/Capacity Core Processing Clovertown RevF-Quad Core Data mining SAP

Aspectos de Planejamento de Capacidade em ambiente x86 Obrigado! [email_address]

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O que há de novo na plataforma x86 para High Performance por Jefferson de A Silva