1. Maths is not everything
Embedded Systems
4 - Hardware Architecture
CPU
Input/Output mechanisms
Memory
Buses and Aux I/O
Input/Output interfaces
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Power Management

2. Maths is not everything
Input/Output
Mechanisms
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3. I/O devices
Usually includes some non-digital
component.
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CPU
status
reg
data
reg
mechanism
Typical digital interface to CPU:

4. Application: 8251 UART
Universal asynchronous receiver
transmitter (UART): provides serial
communication.
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© 2008 Wayne Wolf
8251 functions are integrated into
standard PC interface chip.
Allows many communication parameters to
be programmed.

5. Serial communication
Characters are transmitted separately:
no char
(marking)
stop
start
bit 0
bit 1
...
bit n-1
par
time
Serial communication parameters
Baud (bit) rate.
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Number of bits per character.
Parity/no parity.
Even/odd parity.
Length of stop bit (1, 1.5, 2 bits).

6. 8251 CPU interface
CPU
status
(8 bit)
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data
(8 bit)
xmit/
rcv
8251
serial
port

7. Programming I/O
Two types of instructions can support I/O:
special-purpose I/O instructions;
memory-mapped load/store instructions.
Intel x86 provides in, out instructions.
Most other CPUs use memory-mapped I/O.
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I/O instructions do not preclude memorymapped I/O
It is possible to have memory-mapped I/O on a
x86 architecture...

8. ARM memory-mapped I/O
Define location for device:
DEV1 EQU 0x1000
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Read/write code:
LDR
LDR
LDR
STR
r1,#DEV1 ; set up device addr
r0,[r1] ; read DEV1
r0,#8 ; set up value to write
r0,[r1] ; write value to device

9. MSP430 memory mapped I/O
Start of flash (0xF000)
ORG 0xF000
LED1 EQU BIT3
Reset:
;
;
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Stop:
mov.b
mov.b
mov.b
mov.b
#00001000b, &0x2A ;set port direction
#LED1,&P2DIR
#00001000b, &0x29 ;set output to LED
#LED1,&P2OUT
jmp stop
ORG 0xFFFE
DW Reset
END

10. Peek and poke
Traditional HLL interfaces:
int peek(char *location) {
! return *location;
}
void poke(char *location, char newval){
! (*location) = newval;
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}
used as:
dev_stat= peek(DEV1);
! poke (DEV1, 8);

11. Busy/wait output
Simplest way to program device.
Use instructions to test when device is ready.
char *mystring = “ hello world”;
char *current_char;
current_char = mystring;
while (*current_char != ‘0’) {
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poke(OUT_CHAR,*current_char);
while (peek(OUT_STATUS) != 0);
current_char++;
}

12. Simultaneous busy/wait input and output
while (TRUE) {
! /* read */
! while (peek(IN_STATUS) == 0); /* wait */
! achar = (char)peek(IN_DATA);
! /* write */
! poke(OUT_DATA,achar);
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! poke(OUT_STATUS,1);
! while (peek(OUT_STATUS) != 0);/* wait */
! }

13. Interrupt I/O
Busy/wait is very inefficient.
CPU can’t do other work while testing device.
Hard to do simultaneous I/O.
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Interrupts allow a device to change the
flow of control in the CPU.
Causes subroutine call to handle device.

14. CPU
PC
IR
intr request
intr ack
data/address
status
reg
data
reg
mechanism
Interrupt interface
CPU and device are connected by CPU bus.
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© 2008 Wayne Wolf
CPU and device handshake:
device asserts interrupt request;
CPU asserts interrupt acknowledge when it can
handle the interrupt.

15. Interrupt behavior
Based on subroutine call mechanism.
Interrupt forces next instruction to be a
subroutine call to a predetermined
location.
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Return address is saved to resume executing
foreground program.

16. Maths is not everything
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Example: character I/O handlers
void input_handler() {
! achar = peek(IN_DATA);
! gotchar = TRUE;
! poke(IN_STATUS,0);
}
void output_handler() {
/* nothing has to be done here as
the call to this function implies
the char has been sent */
}

17. Example: interrupt-driven main program
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Maths is not everything
main() {
! while (TRUE) {
! ! if (gotchar) {
! !! poke(OUT_DATA,achar);
! !! poke(OUT_STATUS,1);
! !! gotchar = FALSE;
! !! }
! !}
!}

18. Example: interrupt I/O with buffers
Queue for characters:
a
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head tail
tail

19. Buffer-based input handler
void input_handler() {
! char achar;
! if (full_buffer()) error = 1;
! else {
achar = peek(IN_DATA);
add_char(achar);
}
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Maths is not everything
! poke(IN_STATUS,0);
/* if buffer was empty force sending */
! if (nchars == 1) {
poke(OUT_DATA,remove_char());
poke(OUT_STATUS,1);
}
}

20. I/O sequence diagram
:foreground
:input
:output
:queue
empty
a
empty
b
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bc
c

21. Priorities and vectors
Two mechanisms allow us to make
interrupts more specific:
Priorities determine what interrupt gets CPU first.
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Vectors determine what code is called for each type
of interrupt.
Mechanisms are orthogonal: most CPUs
provide both.

22. Prioritized interrupts
device 1
interrupt
acknowledge
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L1 L2 .. Ln
CPU
device 2
device n

23. Interrupt prioritization
Masking: interrupt with priority lower
than current priority is not recognized
until pending interrupt is complete.
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Non-maskable interrupt (NMI): highestpriority, never masked.
Often used for power-down.

24. Example: Prioritized I/O
:interrupts
B
C
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A
A,B
:foreground
:A
:B
:C

25. Interrupt vectors
Allow different devices to be handled by
different code.
Interrupt vector table:
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Interrupt
vector
table head
handler 0
handler 1
handler 2
handler 3

26. Interrupt vector acquisition
:CPU
:device
receive
request
receive
ack
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receive
vector

27. Generic interrupt mechanism
continue
execution
N
N
ignore
intr?
Y
intr priority >
current
priority?
Y
ack
Y
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N
bus error
Y
timeout?
N
vector?
Y
call table[vector]
Assume priority
selection is
handled before
this point.

28. Interrupt sequence
CPU acknowledges request.
Device sends vector.
CPU calls handler.
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Software processes request.
CPU restores state to foreground
program.

29. Interrupt Service Routines
Look superficially like a subroutine.
However, unlike subroutines
ISR’s can execute at unpredictable times.
Must carry out action and thoroughly clean up.
Must be concerned with shared variables.
Must return using the right instruction
e.g. reti rather than ret in MSP430
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ISR must handle interrupt in such a way that
the interrupted code can be resumed without
error
Copies of all registers used in the ISR must be saved
(preferably on the stack)

30. Interrupt Service Routines
Well-written ISRs:
Should be short and fast
Should affect the rest of the system as little as
possible
Require a balance between doing very little – thereby
leaving the background code with lots of processing –
and doing a lot and leaving the background code with
nothing to do
Applications that use interrupts should:
Disable interrupts as little as possible
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Respond to interrupts as quickly as possible
Communicate w/ISR only through global variables
(never through registers!!!)

31. Debugging interrupt code
What if you forget to change/save registers?
Foreground program can exhibit mysterious bugs.
Bugs will be hard to repeat---depend on interrupt timing.
Interrupt-related runtime problems can be exceptionally
hard to debug !!!
Common interrupt-related errors include:
Failing to protect global variables
Forgetting to actually include the ISR - no linker error!
Not testing or validating thoroughly
Stack overflow
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Running out of CPU horsepower
Interrupting critical code
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Trying to outsmart the compiler

32. Sources of interrupt overhead
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Handler execution time.
Interrupt mechanism overhead.
Register save/restore.
Pipeline-related penalties.
Cache-related penalties.

33. Maths is not everything
Input/Output
ARM Interrupt Mechanisms
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34. ARM interrupts
ARM7 supports two types of interrupts:
Fast interrupt requests (FIQs).
Interrupt requests (IRQs).
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Interrupt table starts at location 0.

35. Maths is not everything
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ARM Modes - registers

36. ARM interrupt procedure
CPU actions:
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Save PC.
Copy CPSR to SPSR.
Force bits in CPSR to record interrupt.
Force PC to vector.
Handler responsibilities:
Restore proper PC.
Restore CPSR from SPSR.
Clear interrupt disable flags.

37. ARM interrupt latency
Worst-case latency to respond to
interrupt is 27 cycles (best is ≈ 4 cycles):
Two cycles to synchronize external request.
Up to 20 cycles to complete current instruction.
Three cycles for data abort.
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Two cycles to enter interrupt handling state.

38. Maths is not everything
Input/Output
MSP430 Interrupt Mechanisms
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39. Interrupts
Interrupts preempt normal code execution
Interrupt code runs in the foreground
Normal (e.g. main()) code runs in the background
Interrupts can be enabled and disabled
Globally
Individually on a per-peripheral basis
Non-Maskable Interrupt (NMI)
The occurrence of each interrupt is unpredictable
When an interrupt occurs
Where an interrupt occurs
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Interrupts are associated with a variety of on-chip and
off-chip peripherals.
Timers, Watchdog, D/A, Accelerometer
NMI, change-on-pin (Switch)

40. Interrupt Flags
Each interrupt has a flag that is raised
(set) when the interrupt occurs.
Each interrupt flag has a corresponding
enable bit – setting this bit allows a
hardware module to request an interrupt.
Most interrupts are maskable, which
means they can only interrupt if
1)
enabled and
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40
2)
the general interrupt enable (GIE) bit is set in the
status register (SR).

41. Interrupt Vectors
The address of an ISR is defined in an
interrupt vector.
The MSP430 uses vectored interrupts where
each ISR has its own vector stored in a
vector table located at the end of program
memory.
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Note: The vector table is at a fixed location
(defined by the processor data sheet), but the
ISRs can be located anywhere in memory.

42. Interrupts
MSP430x2xx Interrupt Vectors
INTERRUPT SOURCE
Power-up
External reset
Watchdog
NMI
Oscillator fault
Flash memory violation
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
NMIIFG
OFIFG
ACCDVIFG
Timer_B3
TBCCR0 CCIFG
TBCCR1 CCIFG
TBCCR2 CCIFG, TBIFG
ADDRESS
SECTION
PRIORITY
Reset
0xFFFE
.reset
15, highest
Non-maskable
0xFFFC
.int14
14
Maskable
0xFFFA
.int13
13
Maskable
0xFFF8
.int12
12
0xFFF6
Timer_B3
SYSTEM INTERRUPT
.int11
11
Watchdog Timer
0xFFF4
.int10
10
TACCR0 CCIFG
TACCR1 CCIFG,
TACCR2 CCIFG, TAIFG
Maskable
0xFFF2
.int09
9
Timer_A3
Maskable
0xFFF0
.int08
8
USCI_A0/USCI_B0 Rx
UCA0RXIFG, USB0RXIFG
Maskable
0xFFEE
.int07
7
USCI_Z0/USCI_B0 Tx
UCA0TXIFG, UCB0TXIFG
Maskable
0xFFEC
.int06
6
ADC10
ADC10IFG
Maskable
0xFFEA
.int05
5
0xFFE8
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Maskable
Timer_A3
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WDTIFG
.int04
4
I/O Port P2
P2IFG.0 – P2IFG.7
Maskable
0xFFE6
.int03
3
I/O Port P1
P1IFG.0 – P1IFG.7
Maskable
0xFFE4
.int02
2
0xFFE2
0xFFE0
.int01
.int00
1
0

43. MSP430F2274 Address Space
Memory
32KB
Address
Description
Access
0xFFFF
0xFFC0
Flash
Size
Interrupt Vector Table
Word
Program Code
Word/Byte
Stack
Word/Byte
0xFFBF
0x8000
SRAM
1KB
0x05FF
0x0200
256
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16-bit Peripherals Modules
Word
240
0x00FF
0x0010
8-bit Peripherals Modules
Byte
16
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0x01FF
0x0100
0x000F
0x0000
8-bit Special Function Registers
Byte

44. Processing an Interrupt…
Current instruction completed
MCLK started if CPU was off
Processor pushes program counter on stack
Processor pushes status register on stack
Interrupt w/highest priority is selected
Interrupt request flag cleared if single sourced
Status register is cleared
Disables further maskable interrupts (GIE cleared)
Terminates low-power mode
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Processor fetches interrupt vector and stores it in
the program counter
User ISR must do the rest!

45. Interrupt Stack
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46. Returning from ISR
MSP430 requires 6 clock cycles before
the ISR begins executing
The time between the interrupt request and the start
of the ISR is called latency
An ISR always finishes with the return
from interrupt instruction (reti) requiring
5 cycles
The SR is popped from the stack
Re-enables maskable interrupts
Restores previous low-power mode of operation
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The PC is popped from the stack
Note: if waking up the processor with an ISR, the new
power mode must be set in the stack saved SR

47. Return From Interrupt
Single operand instructions:
Mnemonic
Operation
Description
PUSH(.B or .W) src
SP-2→SP, src→@SP
Push byte/word source on stack
CALL
SP-2→SP, PC+2→@SP
dst→PC
Subroutine call to destination
TOS→SR, SP+2→SP
TOS→PC, SP+2→SP
Return from interrupt
dst
RETI
Emulated instructions:
Mnemonic
Operation
Emulation
Description
RET
@SP→PC
SP+2→SP
MOV @SP+,PC
Return from subroutine
POP(.B or .W) dst
@SP→temp
SP+2→SP
temp→dst
MOV(.B or .W) @SP
+,dst
Pop byte/word from stack to
destination
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48. Maths is not everything
Input/Output
Privileged Modes
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49. Supervisor mode
May want to provide protective barriers
between programs.
Avoid memory corruption.
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© 2008 Wayne Wolf
Need supervisor mode to manage the
various programs.
MSP430 does not have a supervisor mode.

50. ARM supervisor mode
Use SWI instruction to enter supervisor
mode, similar to subroutine:
SWI CODE_1
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Sets PC to 0x08.
Argument to SWI is passed to supervisor
mode code.
Saves CPSR in SPSR.

51. Exception
Exception: internally detected error.
Exceptions are synchronous with
instructions but unpredictable.
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Build exception mechanism on top of
interrupt mechanism.
Exceptions are usually prioritized and
vectorized.

52. Trap
Trap (software interrupt): an exception
generated by an instruction.
Call supervisor mode.
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© 2008 Wayne Wolf
ARM uses SWI instruction for traps.