Expert carrier

1. Layout Design Methodology
Agenda
I. Advanced Technology
II. Nanometer Solution
III. Library Based Design
IV. Expertise & Architecture
V. Semi-Automation Flow
VI. Summary
Slide 1 July 31, 2009
Love & Passion

2. Reach the Goal
Advanced
Methodology
Traditional
35nMt 70nMt
45nMt 90nMt
Slide 2 Love & Passion July 31, 2009

3. Project Application
• Increased density, performance, and integration
– Increased complexity
Complexity
Advanced
1GB @ 70nm
Traditional
512MB @ 90nm
256MB @ 110nm
Design Cycle (Months)
04 06 08 10 Unacceptable 16
Design Verification Re-Design
12
Slide 3 Love & Passion July 31, 2009

4. Nanometer Solution by Design
Process
Stable
OPC
System &
High Perf.
Circuit Design
Pre-Layout Design Nanometer Effects
& Verification Speed
Physical
Design Quality
Post-Layout
Verification & Analysis Passion
TapeOut to No mistake
Manufacture
Mass Product
Slide 4 Love & Passion July 31, 2009

5. Concept of
Library Based Design
Library • Clean Design products
Device Design
• Detail analysis
The 4th Stage
• Effective detecting of hidden facts
Resource
• High Speed , High Quality
• Shorten Design Cycle
• Verify stable Library
High technology
The 3rd Stage
• Support and cover the process
• Cut down Man power
The 2nd Stage • Improve Programming and flow
• Add elements of Basic Library
• Set up Programming
The 1st Stage • Fix a regular design flow
• Environment, Documentations
• Compose Elemental Library
Slide 5 Love & Passion July 31, 2009

6. Analog Expert
Author: Generator Expert Team (Munich, US and China)
Creation Date: November 2008 II. Analog layout in other circuits
Version: V0.1
Status: Released
3.5.1 Receiver …….………………………………. Page 37
3.5.2 ESD …………..…….. .……………………... Page 41
1. Introduction ……………………………………........... Page 02
4.4 Non-Transistor Devices
2. General …….…………………………....................... Page 04
4.1.1 DT Capacitance…………………………… Page 43
I. Analog layout in Generator circuits
4.1.2 Resistor .……………………………………. Page 46
3.1 References
4.1.3 Diode ….…………………………………… Page 49
3.1.1 VREF Bandgap …….………….…………………. Page 09
4.1 Questions of Analog layout .……………….. Page 50
3.1.1 Current REF…………………….…………………. Page 18
4.2.1 Matching ………………………………….. Page 55
3.1.2 Other References ………………………….. …… Page 20
4.2.2 Noise ………………………………………. Page 61
3.3 Pumps 4.2.3 Parasitic ………………………………….... Page 62
3.3.1 Negative Voltage (VBB/VNWLL/VBURN)……… Page 23
5.1.1 Current Mirrors .….………………………… Page 64
3.3.2 Positive Voltage (VPP)…. … ……….. …………. Page 27
5.1.2 Differential Pairs ………………………….. Page 93
3.4 Regulators
5.2 WN Proximity ………………………………... Page 98
3.4.1 Folded Cascode Amplifier (Vint/ Veql/ Vdll) …… Page 29
5.3 STI Stress ..…….……………..………........... Page 104
3.4.2 Stand-by Generator (VINT/VBLH) …….……….. Page 31
5.4 Design Layout Interaction .………........................ Page 110
3.4.3 Half Voltage (VBLEQ/VPL) .…………………….. Page 33 5.5 Summary .………................................................. Page 111
Page 111
Slide 6 Love & Passion July 31, 2009

7. Architecture
BANK XHOLE BANK
Data Translate
Voltage SPERI & CPERI NPERI
DLL
Auto cell, P & R Data Shrink
BANK XHOLE BANK
 Manual region: BANK, Voltage, I/O and Address Buffers
 Auto Layout Place & Rout: SPERI & CPERI
 Data Shrink from Other Technology: DLL(90nm0.70nm)
Slide 7 Love & Passion July 31, 2009

8. Semi-Automation flow
Virtuoso® schematic
composer
Connectivity Driven
Layout
Net
Information
Connectivity Based
Virtuoso® Layout Editor Editing
And Pcells
+ Align Instances Automated Device
+ Search Net Placement
+ Routing(pcellPath)
+ Create Gardring Gate level
+ Make Terminal(pin) Routing(except TR)
Number of DRC/LVS
DRC/LVS
Errors Significantly
Reduced
Slide 8 Love & Passion July 31, 2009

9. Layout Design Method
Environment Setup
(Tech File/Std. Library)
Design Rule
Schematic
Design Guide
PCell Virtuoso SC
• Array Control/Main Amp
• Fuse/PAD/ESD
Classify Cell • Power Block/Power Rail
LVS/DRC • Chip Guard/ XY-Hole
Check File Setup SKILL
Peripheral Cell Manual Cell
SKILL Program To Make this flow
Is on development automatically, We
must use Library
Based Automation
SKILL Programs have
been developed
Assemble Top Block Peripheral Block Manual Block
Virtuoso XL Virtuoso LE Virtuoso LE
Virtuoso LE SKILL
SKILL, ICC
Replace Real Block
Virtuoso LE
LVS/DRC by Assura, Calibere Thickness Time Taking Flow
Process Pattern Add LVS DRC/PG
SKILL
Slide 9 Love & Passion July 31, 2009

10. Summary
• Correlation between Simulation and Layout
• Timing optimization right now
• Disruptive Technologies
• Possibility of profound impact on design
methodology
• Wave of the future is here!!
Slide 10 Love & Passion July 31, 2009