Juniper Networks Router Architecture [Scholarly Paper Presentation]

1. Juniper Networks Router Architecture [NGN Router OS] Scholarly Paper Presentation (In partial fulfillment for MS Degree in Computer Engineering) Advisor: Dr. Jeremy Allnutt Co-advisor: Dr BijanJabbari George Mason University, Fairfax, Virginia Lawrence Awuah lawuah@gmu.edu ljawuah@ieee.org Fall 2007

3. Architecture Overview

4. Specific TX Matrix & T640 Routing node Implementation

5. Packet Forwarding and ASIC Design

7. Routers operate in two different planes:Control Plane The control plane defines the part of the router architecture that is concerned with generating the networkrouting table. Control Plane processing leads to the construction of RIB and FIB in memory. Forwarding Plane The forwarding plane is responsible for packet forwarding. This planeis responsible for processing packets in hardware before forwarding them across the switch fabric from the ingress interface to the appropriate egress interface - HS packet processing.

9. Bandwidth density

10. Security

11. Single software image

12. Multi-chassis capability

13. IP service delivery

14. High availability

15. Expandable average lifetimeLeading to CAPEX & OPEX savings - replacing old equipment vs. installing new equipment every few years + operational cost.

19. A set of dynamically loadable applications with their own separate and protected memory spaces – security, flexibility, speed.

21. Minimal operating system kernel.

22. Most operating-system services are provided in user-mode - functions such as the host stack, device drivers, or file system run in user mode.

24. Minimal system downtime.

25. Graceful restart and gracefuldegradation capabilities.

26. Dynamic loading and start/stop capability allows frequent system refresh cycles.

27. Kernel-loadable modules.

28. Kernel protection and security.

31. T640 Routing Nodes (4 maximum)

32. maintains distributed packet forwarding decisions

33. also known as line-card chassis (LCCs) providing network interfaces for the routing matrix

34. A TX Matrix platform

35. executes the routing protocols for the routing matrix and maintains system state

36. provides services to switch fabric that interconnects the individual T640 routing nodes also know as the switch-card chassis (SCC)

37. A set of cables

43. Four operationally independent, identical and active switch planes.

45. Egress PFE drops packets if cells missing (assigned sequence #s).

47. Real-time CPU scheduling such as preemptive priority-based, preemptive kernel (for sensitive applications such as voice and video).