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FPL 2018: A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs

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LEGATO project
LEGATO project

Poster presented at 2018 International Conference on Field Programmable Logic and Applications (FPL)

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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs Behzad Salami(1,2), Osman Unsal(2), and Adrian Cristal(1,2,3) (1) Barcelona Supercomputing Center (BSC) (2) Universitat Politècnica de Catalunya (UPC) (3) IIIA - Artificial Intelligence Research Institute CSIC - Spanish National Research Council Undervolting • Meaning: Aggressive voltage underscaling below the nominal-level. • Objective: Achieve energy-efficiency. • Overhead: timing faults  reliability. • Our contribution: Undervolting on Xilinx FPGAs, focused on BRAMs. ZC702 VC707 KC705 Power&Reliability DemoSetup Fault Variability of BRAMs Power/Energy Efficiency Reliability Main Behavior of Xilinx FPGAs • Large voltage guardbands exists, i.e., 39% of the nominal-level, confirmed for multiple platforms. • Power consumption is significantly reduced (10X). • Below voltage guardband, fault rate exponentially increases. • There is a system crash voltage point, beyond which FPGA stops operating. FaultVariationMap Fault Characterization • Significant fault variability between BRAMs. • Permanent fault behavior. • Fault Inclusion Property (FIP).

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