LogicMindtech Nologies

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LogicMindtech Nologies

Trade offs for threshold implementations

Single supply 3 t gain-cell for low-voltage low-power applications

Result biased distributed-arithmetic-based

Reliable and error detection architectures of pomaranch for false alarm-sensitive cryptographic applications

Novel design algorithm for low complexity

Non binary orthogonal latin square codes for a multilevel phase charge memory (pcm)

Low power programmable prpg with test

Low power and area-efficient shift register using pulsed latches

Low cost high-performance vlsi architecture for montgomery modular multiplication

Input based dynamic reconfiguration of

Improved 8 point approximate dct for image and video compression requiring only 14 additions

Input vector monitoring concurrent bist architecture using sram cells

Improved 8 point approximate dct for image and video compression requiring only 14 additions

High throughput multistandard transform core supporting mpeg h 264 vc 1 using common sharing distributed arithmetic

High throughput finite field multipliers using redundant basis for fpga and asic implementations

High speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels

Graph based transistor network generation

Fully reused vlsi architecture of fm0 manchester encoding using sols technique for dsrc applications

Fault tolerant parallel ff ts using error correction codes and parseval checks

Fast sign detection algorithm for the rns moduli set {2n+1 − 1, 2n − 1, 2n}