4. Multistep Processing of a User Program

7. Dynamic relocation using a relocation register

11. Overlays for a Two-Pass Assembler

13. Schematic View of Swapping

15. Hardware Support for Relocation and Limit Registers

21. Address Translation Architecture

22. Paging Example

23. Paging Example

24. Free Frames Before allocation After allocation

27. Paging Hardware With TLB

30. Valid (v) or Invalid (i) Bit In A Page Table

34. Two-Level Page-Table Scheme

37. Hashed Page Table

39. Inverted Page Table Architecture

41. Shared Pages Example

43. User’s View of a Program

44. Logical View of Segmentation 1 3 2 4 user space physical memory space 1 4 2 3

48. Segmentation Hardware

49. Example of Segmentation

50. Sharing of Segments

52. MULTICS Address Translation Scheme

54. Intel 30386 Address Translation