IBIS is a standard for describing the analog behavior of digital device buffers using plain ASCII text. Go through the slides and find out more on this.

1. EMI Analyst™
EMI ANALYST™ Software Suite
I n t u i t i v e  A c c u r a t e  E f f e c t i v e
How to use IBIS files in EMI Analyst™
IBIS – Input/Output Buffer Information
Specification

2. EMI Analyst™
What is an IBIS File?
• IBIS is a standard for describing the analog behavior of digital device
buffers using plain ASCII text.
• IBIS files are not really models, they contain data used for modeling. IBIS is really a
specification.
• Simulation tools interpret IBIS specifications to implement their own models and
algorithms.
• IBIS defines component properties in terms of behavior instead of circuitry.
• Spice models are limited to small signals.
• IBIS covers entire operating range, plus clamping of over- and under voltage
transients, making it possible to model ringing that overshoots or undershoots.
• IBIS does not reflect the product’s interior logic and interactions, only the
behavior of the circuits connected to the device pins.

3. EMI Analyst™
What Is Needed for an EMI Analyst™ Model?
For example, LVDS circuit
Outputs DO+/DO-
• Output Impedance
• Cpin, Rpin, Lpin
• C_comp
• Rout
• Rise/Fall Time Waveforms
• Rising waveform
• Falling waveform
Inputs RI+/RI-
• Input Impedance
• Cpin, Rpin, Lpin
• C_comp
• Rin

4. EMI Analyst™
IBIS Output and Input Models
VDD
Output +
Output -
GND
Input/
Enable
Pins
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Internal
Logic
VDD
In Pin
GND
C_comp
C_comp
LpinRpinCpin
LpinRpinCpin
LpinRpinCpin
VDD
Input +
GND
Output
Pin
Input -

5. EMI Analyst™
Pin Parasitics – Rpin, Lpin, Cpin
• Outputs
• Inputs
Out Pin
C_comp
Lpin Rpin Cpin
C_comp
LpinRpinCpin
In Pin

6. EMI Analyst™
Output Model Input Model
DO+, DO- RI+, RI-

7. EMI Analyst™
LVDS Waveform Specs
• Constant current: 4.0 mA nom.
• Some mfg. use 3.5 mA
• Char. Z: 100 ohms nom.
• Output voltage: ±400 mV nom.
• Offset voltage: 1.2V (Vref)
• VOH = 1.4V, VOL = 1.0V
• Rcvr input threshold voltage:
±100 mV nom.
• Rcvr max. CM voltage: ±1V min.

8. EMI Analyst™
Output Impedance and Input Impedance
Output Z from datasheet
Rout = 58 ohms (350 mV / 6 mA)?
Input Z from datasheet
Rin = 2.4 Mohm (2.4V / 1uA)?
= 240 kohm (2.4V / 10 uA)?
Input and output impedance change dynamically with signal amplitude
From IBIS model, output impedance is about 230 ohms in operating range

9. EMI Analyst™
Pullup Curve
I-V curve for VOH
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin

10. EMI Analyst™
Pulldown Curve
I-V curve for VOL
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin

11. EMI Analyst™
Output Model – Power Clamp
I-V curve when output pin is pulled above VCC
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin

12. EMI Analyst™
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin
Output Model – Ground Clamp
I-V curve when output pin is pulled below GND

13. EMI Analyst™
Output Model – Rising Waveform
20% - 80% (1.08V – 1.32V): 700 ps
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin

14. EMI Analyst™
Output Model – Falling Waveform
80% - 20% (1.32V – 1.08V): 390 nsec
Rising
Ramp
(V-t)
Pullup
(V-I)
Power
Clamp
(V-I)
Ground
Clamp
(V-I)
Pull-
Down
(V-I)
Falling
Ramp
(V-t)
Internal
Logic
VDD
Out Pin
GND
C_comp
C_comp
Lpin Rpin Cpin
Lpin Rpin Cpin
Lpin Rpin Cpin

15. EMI Analyst™
DM Waveform from IBIS File
Create data file from IBIS values and import into EMI Analyst™ Source form.

16. EMI Analyst™
Input Model – Power Clamp
I-V curve when input pin is pulled above VCC

17. EMI Analyst™
Input Model – Ground Clamp
I-V curve when input pin is pulled below GND

18. EMI Analyst™
LVDS Circuit and Equivalent Model
LVDS Circuit Model
Equivalent Circuit from IBIS File and Datasheet
DO+
DO-
RI+
RI-
100Ω
50m1.05193n
0.16890p
58
50m1.05308n
0.16861p
58
DO+
DO-
RI+
RI-
100Ω
50m 1.05193n
0.16890p
240k
50m 1.64135n
0.37335p
240k
4.13p
4.13p
3.56P
3.56P
Z0 = 100 Ω
1p

19. EMI Analyst™
Predicted Radiated Emissions for Shielded
LVDS Cable with no Common Mode Voltage

20. EMI Analyst™
References
• The IBIS model, Part 1: A conduit into signal-integrity analysis
http://www.ti.com/lit/an/slyt390/slyt390.pdf
• The IBIS model, Part 2: Determining the total quality of an IBIS model
http://www.ti.com/lit/an/slyt400/slyt400.pdf
• The IBIS model, Part 3: Using IBIS models to investigate signal-integrity issues
http://www.ti.com/lit/an/slyt413/slyt413.pdf
• IBIS reader: https://www.mentor.com/pcb/downloads/visual_ibis_editor/