A brief presentation on behavioral synthesis and systemC.

1. Presentation on-
Behavioral Synthesis &
System C
Presented by-
Mukit Ahmed Chowdhury (14-97963-2)

2.  Behavioral synthesis
 SystemC

3.  What is behavioral synthesis?
 Why behavioral synthesis?
 Synthesis procedure
 Data flow optimization
 Scheduling
 Clustering
 Allocation and binding
 Control logic generation
 limitations

4.  A synthesis process where behavior of a
hardware is described.
 Gates etc are not defined or controlled by
the designer.
 Not specific for a certain type of technology.
 Easier to use, but control over the design is
less.

5.  Complicated constraints
 timing constraints
 bus protocols
 pipelining
 physical constraints
 registers and ALUs are expensive
 communications (muxes, wiring) are expensive
 packaging hierarchy
 Heterogeneity
 separation of data and control logic
 wide range of RTL primitives
(ALU, ROM, MUX)

6.  Parse behavioral description into data flow graph
 equivalent to compiler intermediate code
 Optimize data flow graph
 compiler-like operations
 Schedule operations
 assign operations to clock cycles (in synchronous system)
 Cluster operations
 group connected components together
 Allocate RTL resources
 place values in registers
 place operations in ALUs
 data transfers on wires and MUXs
 Generate control logic
 microcode, PLA, random logic
 fit to clock cycles

7.  Transform data flow
 minimize cost (operations)
 minimize delay (path length)
 Compiler-like transformations
 loop unrolling
 code motion
 strength reduction

8.  Assign operations to clock cycles
 balance speed vs. cost
D
B C
AA
1
2
3
D
B
C
A
A
3
4
5
1
2
• 3 clock cycles
• 2 ALUs
• 5 clock cycles
• 1 ALU

9.  Cluster operations based on connectivity
 connected components
 Uses
 guide later package partitioning
 guide binding to RTL modules
 guide chip place and route

10.  Map data flow to RTL components
 allocate operator and register components
 bind operations and values to them
 minimize total cost of components
 Cost models
 cost for different operators
 cost for register bits
 determined by RTL implementation experience
 Approach
 NP-hard search problem
 related to graph covering
 cover data flow graph with RTL modules
 minimax - EMUCS
 maximum munching - like code generation
 tricky trade-offs
 e.g. adder and subtractor vs. one ALU

11.  State Machine
 transformed along with data flow
 specify clock cycles, signal values
 inputs from conditionals
 outputs for muxes, ALUs, etc.
 Clocking
 gating clocks with control values
 Approach
 ROM microcode
 PLA state machines
 random logic state machines
 state assignment, optimization left for RTL synthesis

12.  Easier to use
 No need to think about what are the
components to be used, just describe the
desired behavior
 Limits designer to specify parts, component
types etc.
 For a tailored chip, consumers often have
certain specifications which might not be
met by behavioral synthesis.

13.  What is System C
 History
 Language features
 How System C works
 System C vs System Verilog
 Vendors supporting System C
 Conclusion

14.  C++ with HDL features.
 A set of classes and macros which can
provide event driven simulation interfaces.
 Can simulate concurrent processes described
in plain c++ syntax.
 Object oriented design partitioning and
template classes
 Can use all the data types offered in c++ and
some other ones supported by system c
library.

15. In simple words, system c is actually c++
language developed to be used as a HDL. It is
more likely to be a system level modeling
language.

16.  1999: ARM Ltd., COware, Synopsys and CynApps
teamed up to develop SystemC (CynApps later
became Forte Design Systems) to launch its first
draft version in 1999.
 27th September, 1999: open systemC initiative
announced.
 1st March,2000: systemC V0.91 released.
 28th March,2000: systemC V 1.0 released.
 12th December, 2005: IEEE approved the
IEEE1666-2005 standard for systemC.
 10th November, 2011: IEEE approved the
IEEE1666-2011 standard for systemC.

17.  Modules
Modules are the basic building blocks of a SystemC
design hierarchy. A SystemC model usually consists of
several modules which communicate via ports. The
modules can be thought of as a building block of
SystemC.
 Ports
Ports allow communication from inside a module to
the outside (usually to other modules) via channels.
 Exports
Exports incorporate channels and allow
communication from inside a module to the outside
(usually to other modules).
 Processes
Processes are the main computation elements. They
are concurrent.

18.  Channels
Channels are the communication elements of
SystemC. They can be either simple wires or
complex communication mechanisms
like FIFOs or bus channels.
 Elementary channels:
signal: the equivalent of a wire
buffer
fifo
mutex
semaphore
 Interfaces
Ports use interfaces to communicate with
channels.

19.  Events
Events allow synchronization between processes
and must be defined during initialization.
 Data types
SystemC introduces several data types which
support the modeling of hardware.
Extended standard types:
sc_int<n> n-bit signed integer
sc_uint<n> n-bit unsigned integer
sc_bigint<n> n-bit signed integer for n>64
sc_biguint<n> n-bit unsigned integer for n>64
 Logic types:
sc_bit 2-valued single bit
sc_logic 4-valued single bit
sc_bv<n> vector of length n of sc_bit
sc_lv<n> vector of length n of sc_logic

20.  Fixed point types:
sc_fixed<> template signed fixed point
sc_ufixed<> template unsigned fixed point

21.  Native c/c++ types
 Data types for system modeling
 2 value (0/1) logic and logic vector
 4 value (0,1, Z, X) logic and logic vector
 Signed and unsigned integer
 Fixed point types

25. SystemC System Verilog
•(C++) + Hardware modeling
(Concurrency, timing, signal,
port, etc)
•Popular in Research Areas
•Most Benchmark models are
also written in C
•Good for modeling and
designing of huge and complex
digital system
•Good features of higher
language like Polymorphism
•Learning effort: Easier (for
New)
•Extension of Verilog which is
familiar with Verilog engineer
•Popular in Industry
•Many hardware based libraries
• Synthesizable
•Learning effort: Middle (for
New)
•Not good for hardware
modeling as much as VHDL
•Not good for modeling and
designing huge size system
(Complexity of design is higher
than SystemC)

26.  Aldec
 Cadence Design Systems
 Confluent Design
 CoWare
 Forte Design Systems
 Mentor Graphics
 OVPsim: provided by Open Virtual Platforms initiative
with over 100 embedded processor core models used
in SystemC based virtual platforms
 NEC CyberWorkBench
 Synopsys
 Catapult C from Calypto supports SystemC, C++ and C
as input, and also generates SystemC for verification.

27.  Behavioral synthesis: considers behavior of
the system, easy, less control over design.
 systemC: HDL in c++, easy to learn, popularly
used in researches, allows features from high
level programming.

28.  1666-2005 — IEEE Standard System C Language Reference
Manual. 2006. doi:10.1109/IEEESTD.2006.99475. ISBN 0-7381-
4871-7.
 J. Bhasker, ”A SystemC Primer”, Second Edition, Star Galaxy
Publishing, 2004. ISBN 0-9650391-2-9
 Frank Ghenassia (Editor), ”Transaction-Level Modeling with
SystemC: TLM Concepts and Applications for Embedded
Systems”, Springer 2006, ISBN 0-387-26232-6
 www.forteds.com
 A presentation on-” Transaction level communication between
systemC and system verilog”, presented by- Rich Edeleman and
Mark Glasser, Verification technologists, Mentor Graphics.

29. QUESTIONS?
mukit_ahmed@outlook.com