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- 2. ” (Processor) “ “ ” ” CPU“ ” CPU (Processor) “ ” , ALU , Control ,
- 3. CPU Intel
- 4. CPU AMD
- 5. CPU
- 7. Arithmetic & Logical Unit : ALU , Control Unit: CU Memory Arithmetic & Logical Unit : ALU Arithmetic Logic Numeric Character 0-1, - - ALU ALU Multi-Processor
- 8. Control Unit Bus Control Bus,Data Bus Address Bus ALU, , (Central Processing Unit: CPU) Main Memory
- 9. CISC RISC / . . 1990 2 CISC : Complex Instruction Set Computing RISC : Reduces Instruction Set Computing
- 10. CISC : Complex Instruction Set Computing Cycle CISC Pentium 4
- 11. RISC : Reduces Instruction Set Computing RISC : Reduces Instruction Set Computing Pipeline CISC CISC RISC
- 12. RISC RISC 1 One Instruction per Cycle RISC 1 1 Clock Cycle pipeline 1 1
- 13. RISC RISC 1
- 14. RISC RISC Instruction Fixed Instruction Length 1 RISC 1 Word CPU RISC Word 32 Bit 1 Word , Operation, Operand , Result
- 15. RISC RISC load store RISC Operand Register 1 Word Operand 2 load store traffic
- 16. RISC RISC RISC 2 Register Register Indirect Index Register Register Register Index Operation
- 17. CISC CISC RISC RISC CISC RISC 1 1 CISC 100 1 CISC Program CISC Processor Program CISC RISC Processor Processor Processor CISC RISC
- 18. CISC 7 9 RISC 7 9 7 9 1 9 Compiler 9 7 7 CISC 5 7 9 5 4 3
- 19. CISC CISC (Complex RISC RISC (Reduce Instruction Instruction Set Computer) Set Computer) (CISC) (RISC) CISC RISC ( 128 FIX , , , ) CODE 128 BIT 2 6 6 BIT BIT FIX CODE 6 CISC 1 BIT 6 BIT Memory Waste Space RISC FIX CODE Memory
- 20. CISC RISC CISC (Complex RISC (Reduce Instruction Instruction Set Computer) Set Computer) (CISC) (RISC) 1 CISC Complex 1 CISC Instruction RISC RISC CISC LOAD STORE LOAD Polynomial REGISTER CISC REGISTER CLOCK STORE RISC MEMORY 2 Computer DECODE CPU , REGISTER , CISC MEMORY , DISK 2 CLOCK CYCLE FIX-ENCODING DECODE 3 RISC REGISTER
- 21. CISC CISC (Complex RISC RISC (Reduce Instruction Instruction Set Computer) Set Computer) (CISC) (RISC) CISC RISC 128 CPU CPU CODE LOAD STORE Compiler MEMORY REGISTER CPU Compiler Software Support Hardware Compiler CPU Hardware RISC RISC Software CPU Compiler Complex Instruction CISC
- 22. CISC RISC 1. CISC (Complex Instruction Set Computer) CISC - Addressing Mode) Instruction Type) - - CISC Addressing Mode - -
- 23. CISC RISC 2. RISC (Reduce Instruction Set Computer) RISC - - - - - - - -
- 24. RISC Computer 1. 2. 3. 1 instruction format 4. orthogonal ( Overlap instruction ) 5. 1 Addressing Mode
- 25. RISC Computer 6. Load and Store Architecture ( Load Store register – to – register instruction) 7. Instruction set Architecture (ISA) data type 2 integer floating point 8. execute 1 clock cycle 9. RISC chip Strength Software 10. registers Speed CPU (Speed up)
- 26. CISC RISC CISC RISC CISC , RISC CISC RISC
- 27. CISC RISC – – Overlap) – Pipelining Superscalar – Fetch) – Execute) – Superscalar)
- 28. CISC : Motorola MC68000 • • CPU register • Memory
- 29. CISC : Motorola MC68000 Addressing Mode
- 30. CISC : Motorola MC68000 MC Instruction Formats
- 31. RISC : The SPARC • SPARC • Integer register Floating-point register • Branch delay (PC) • Processor state • • (IR) • • MMU (Memory Mapping Unit)
- 32. RISC : The SPARC
- 33. RISC : The SPARC
- 34. RISC : The SPARC SPARC Addressing Mode • register register • register sign-extended, immediate -bit constant
- 35. RISC : The SPARC SPARC Instruction Formats
- 36. RISC : The SPARC Address (Addressing Modes) • Immediate Addressing Mode 8 16 ( op-code ) 8 -128 ( 80H ) 127 ( 7FH ) 16 -32768 ( 8000H ) 32767 ( 7FFFH ) 8 16 0 8 255 ( 0FFH ) 16 65535 ( 0FFFFH )
- 37. RISC : The SPARC Address (Addressing Modes) • Register Addressing Mode • 8088 8 16 1. MOV AX,CX 2. INC AX 3. ADD SI,CX 4. DEC DX
- 38. RISC : The SPARC Address (Addressing Modes) • Direct Addressing Mode Direct addressing mode EA op-code 8088 EA • Register Addressing Mode register indirect addressing EA BX, BP register indirect addressing mode
- 39. RISC : The SPARC Address (Addressing Modes) • Base Relative Addressing Mode base relative addressing mode EA BX BP • Direct Indexed Addressing Mode direct indexed addressing mode EA DI SI
- 40. RISC : The SPARC Address (Addressing Modes) • Base Indexed Addressing Mode base indexed addressing mode Ea base indexed addressing mode 2
- 44. (Direct Addressing) B 01010101 B
- 45. (Direct Addressing) 2 1 256
- 46. (Direct Addressing) 1 2
- 48. Inherent Addressing) • 1 (inherent) implied address) MOV A
- 49. 6800 6800
- 50. 6800 • 2 1 • 1 86 04 ( 2 04
- 51. 6800 • 1 96 00F2 ( 2 F2 A
- 52. 6502 • 6502 MOS Technology) 6800 6502 6800 6502 8 X Y( 6800 16 SP 8 9800 SP 16 6502 • 9800 • absolute mode) 6502 6800
- 53. 6502
- 54. 6502 • 6502 6800 6502 4 X Y 1. (base page indexed mode) X 256 255 (FF ( 11111111) 100000001 8 00000001
- 55. 6502 1 B5 2 02 02 X
- 56. 6502 (pre - indexed indirect mode) X 16 X 64 K 16
- 57. 6502 • 1 A1 2 05 05 X • X 50 ( 50 0055 0055 0056 64 K
- 58. 6502
- 59. 6502 (post - indexed mode) 16 Y
- 60. 6502 1 B1 2 05 07 Y 0007 0007 0008 16 0007 0008 0150 Y 02 0150 + 02 = 0152 Y
- 61. 6502 4. absolute indexed mode) 6502 6800 6800 8 16 6502 16 8
- 62. 6502 1 BD 2 02 2A08 3 2A X
- 63. 6502 • (implied mode) 6502 6800 • 00FF 0350 0351 0400 0050 50 0051 03
- 64. 6502
- 65. : , MCS-51 . : TBS Product, 2547 http://rossukhon.blogspot.com/2007/08/processor-central-processing-unit-cpu.html http://it.excise.go.th/asr2.htm#top http://kanokporn-kcom.blogspot.com/2011/11/processor.html http://www.bcoms.net/hardware/cpu.asp http://lailao2007.tripod.com/cpu.htm http://www.sorncomputer.com/index.php?topic=3.0 http://noolek03.exteen.com/20080726/entry?n=y http://blog-azmeeit.blogspot.com/ http://library.uru.ac.th/webdb/images/RISCCISC.html
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