NECST Lab @ Politecnico di Milano

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The NECST Lab (Novel, Emerging Computing System Technologies Laboratory), The System Architecture Group lab, gathers several different research themes, from the previously existing labs MICROLab and VPLab. It comprises a number of different research lines on advanced topics in computing systems, ranging from architectural characteristics, to hardware-software codesign methodologies, to security and dependability issues of complex system architectures (scaling from mobile devices to large virtualized datacenters). Furthermore, the laboratory pursues its “historical” tradition of research in the definition of methodologies and techniques regarding testability, and fault tolerance.

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Architectural Optimizations for High Performance and Energy Efficient Smith-Waterman Implementation on FPGAs Using OpenCL

il y a 6 ans • 115 Vues

NECST Lab @ Politecnico di Milano

Présentations

DReAMS Research Line Presentation

ORCA Research Line Presentation

STeEL Research Line Presentation

NECST @ Microsoft

A Scalable Dataflow Implementation of Curran's Approximation Algorithm

Self-adaptive container monitoring with performance-aware Load-Shedding policies

Self-adaptive container monitoring with performance-aware Load-Shedding policies

A performance-aware power capping orchestrator for the Xen hypervisor

HUGenomics: a support for personalized medicine research

Fast Algorithms for Quantized Convolutional Neural Networks

Exploit FPGA-based Systems from Data Science High Level Languages

XeMPUPiL: Towards Performance-aware Power Capping Orchestrator for the Xen Hypervisor

A Highly Parallel Semi-Dataflow FPGA Architecture for Large-Scale N-Body Simulation

Self-adaptive container monitoring with performance-aware Load-Shedding policies

earning by s/doing/h4ck1ng/ - Our experience learning application security through hacking competitions

CNNECST: an FPGA-based approach for the hardware acceleration of Convolutional Neural Networks

Exploit FPGA-based Systems from Data Science High Level Languages

CNN Dataflow Implementation on FPGAs

CAOS Demo: Vessel Segmentation Example

Fast Algorithms for Quantized Convolutional Neural Networks

A CAD Framework for FPGA-Based Systems

Self-adaptive container monitoring with performance-aware Load-Shedding policies

XeMPUPiL: Towards Performance-aware Power Capping Orchestrator for the Xen Hypervisor

TiReX: a Tiled Regular eXpression matching architecture

CNN Dataflow Implementation on FPGAs

A CAD Framework for FPGA-based Systems

Architectural Optimizations for High Performance and Energy Efficient Smith-Waterman Implementation on FPGAs Using OpenCL

Fast Algorithms for Quantized Convolutional Neural Networks

NNECST: an FPGA-based approach for the hardware acceleration of Convolutional Neural Networks

Self-adaptive container monitoring with performance-aware Load-Shedding policies