1. CMOS

2. INTRODUCTION
 Integrated circuits: many transistors on single chip.
 Metal Oxide Semiconductor (MOS) transistor
Fast, cheap, low-power transistors
Complementary: mixture of n- and p-type leads to
less power

3. INTRODUCTION
MOSFET
NMOS PMOS CMOS

4. MOSFET
Gate
Drain Source
Metal Oxide Semiconductor Field Effect Transistor
Source ( Phosphorous, Boron)
Drain ( Phosphorous, Boron)
Gate (Aluminum, Polysilicon)

5. NMOS
P-type substrate
N-type dopant for Source & Drain
Inversion layer is formed to conduct electricity

6. PMOS
N-type substrate
P-type dopant for Source & Drain
Inversion layer is formed to conduct electricity

7. CMOS
A combination of both NMOS & PMOS technology
Most basic example: inverter

8. PROCESS FLOW
WELL FORMATION
ISOLATION FORMATION
TRANSISTOR MAKING
INTERCONNECTION

9. CMOS FABRICATION PROCESS
well formation
Start with clean p-type substrate (p-type
wafer)

10. CMOS FABRICATION PROCESS
well formation
Grow epitaxy layer (made from SiO2) as mask
layer for well formation

11. CMOS FABRICATION PROCESS
well formation
Well will be formed
here
By photolithography and etching process,
well opening are made
photolithography and etch processes are shown in next slides

12. PHOTOLITHOGRAPHY (CED)
photoresist
Si02 Photoresist coating (C)
P-substrate
UV light Masking and exposure under
mask
UV light(E)
Resist dissolved after
Opaque
area
developed (D)
P-substrate ◦ Pre-shape the well pattern at
Transparent
area resist layer

13. ETCHING
Removing the unwanted pattern
P-substrate by wet etching
Resistclean
Desired pattern formed
P-substrate

14. CMOS FABRICATION PROCESS
well formation
Phosphorus ion
Ion bombardment by ion implantation
SiO2 as mask, uncovered area will exposed
to dopant ion

15. CMOS FABRICATION PROCESS
Isolation formation
Thick oxide
IncreaseSiO2 thickness by oxidation at high
temperature
Oxide will electrically isolates nmos and
pmos devices

16. CMOS FABRICATION PROCESS
transistor making
nmos will pmos will
be formed be formed
here here
By photolithography and etching process,
pmos and nmos areas are defined

17. CMOS FABRICATION PROCESS
transistor making
Gate oxide
Grow very thin gate oxide at elevated
temperature in very short time

18. CMOS FABRICATION
PROCESS
transistor making
polisilicon
Deposit polisilicon layer

19. CMOS FABRICATION
PROCESS
transistor making
gate
Photolithography (photo) and etching to
form gate pattern

20. CMOS FABRICATION
PROCESS
transistor making
Arsenic ion
photoresist
Photo process to define the nmos active
(source and drain) area and VDD contact
Ion implantation with Arsenic ion for n+
dopant.
Photoresist and polysilicon gate act as
mask

21. CMOS FABRICATION PROCESS
transistor making
VDD
source drain contact
Nmos’s Source and drain with VDD contact
formation
Resist removal

22. CMOS FABRICATION
PROCESS
transistor making
Boron ion
photoresist
Photo process to define the GND contact
and pmos active area (source and drain)
Ion implantation with boron for p+
dopant
Photoresist and gate act as mask

23. CMOS FABRICATION
PROCESS
transistor making
GND
contact Pmos’s Pmos’
drain source
Pmos’s source and drain formation with
GND contact
Resist removal

24. CMOS FABRICATION
PROCESS
interconnection
CVD
Oxide
Deposit CVD Oxide layer through out
wafer surface

25. CMOS FABRICATION PROCESS
Interconnection
contact
Photo and etching process to make contact

26. CMOS FABRICATION PROCESS
interconnection
Metal 1
Metal 1 deposition throughout wafer
surface

27. CMOS FABRICATION
PROCESS
interconnection
Photo and etching processes to pattern
interconnection

28. ADVANTAGES
 High operating speed
 Low cost
 Very low static power consumption
 High degree of noise immunity.

29. DISADVANTAGES
Optical lithography is limited by the light frequency.
Material limitations
Space limitations

30. APPLICATIONS
Integrated Circuits
Data converters
Integrated transceivers
Image sensors
Logic circuits

31. CONCLUSION
 CMOS Transistors are stack of gate, oxide, silicon
 Build logic gates out of switches
 Draw masks to specify layout of transistors