- The document discusses the MIPS R8000 CPU architecture used in SGI workstations and discusses issues with panic errors related to TLB and PTE entries on OpenBSD for the SGI IP26 platform.
- It provides code snippets from OpenBSD showing functions and assembly related to the MIPS64 TLB, cache, and exception handling implementations for the R8000.
- The discussion focuses on troubleshooting a "utlbmod" panic error seen at boot by examining the TLB and PTE implementations in OpenBSD for the R8000 CPU.
15. ?
Set name(s)? (or 'abort' or 'done') [done]
Cannot determine prefetch area. Continue without verification? [no] yes
Installing base57.tgz 100% |**************************| 56003 KB 03:49
Extracting etc.tgz 100% |**************************| 110 KB 00:00
Location of sets? (disk http nfs or 'done') [http] done
Are you *SURE* your install is complete without 'bsd.IP26'? [no] yes
Time appears wrong. Set to 'Sun Sep 6 08:56:36 JST 2015'? [yes]
Saving configuration files...done.
Making all device nodes...sh(8003) in realloc(): error: chunk info corrupted
Abort trap
done.
Installing boot loader in volume header.
Writing file /mnt/usr/mdec/boot-IP26
sgivol: stat /mnt/usr/mdec/boot-IP26: No such file or directory
WARNING: Boot install failed. Booting from disk will not be possible
IP26 RAM disk kernel RAM disk kernel netboot
(ftp.jaist.ac.jp ) base57.tgz
OpenBSD IP26
base57.tgz ” ”
16. ?
/src/distrib/sgi/ramdisk/install.md
md_installboot() {
local _disk=$1
echo "Installing boot loader in volume header."
if ! /usr/mdec/sgivol -w boot /mnt/usr/mdec/boot-$IPARCH $_disk; then
echo "nWARNING: Boot install failed. Booting from disk will not be possible"
fi
for _k in /mnt/bsd{,.mp,.rd}; do
[[ -f $_k.$IPARCH ]] && mv $_k.$IPARCH $_k
done
}
36. …
The 2 in the original code is log2(pte size); k0 >> PAGE_SHIFT will be
the pte number. But in the page table, it is stored as an array of
32-bit words, so we need to shift it to the left by 2. The original
instructions:
PTR_SRL k0, PAGE_SHIFT - 2
andi k0, ((NPTEPG / 2) - 1) << 2
are equivalent to:
PTR_SRL k0, PAGE_SHIFT
andi k0, (NPTEPG / 2) - 1
PTR_SLL k0, 2
and guarantees the address is correctly aligned for the `lwu'
instruction later.