Parth Pandya
2 SlideShares 3 Abonné
Personal Information
Entreprise/Lieu de travail
Hyderabad Area, India India
Profession
Verification Engineer at Xilinx
Secteur d’activité
Electronics / Computer Hardware
À propos
Functional Verification Engineer with experience in development of verification environment, testcases for module and system level verification. Experience in understanding and debugging verilog behavioral design.
Coordonnées
Mots-clés
uvm bit bash register model
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Sv assertion

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UVM Ral model usage

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UVM Ral model usage

Parth Pandya • il y a 9 ans
Personal Information
Entreprise/Lieu de travail
Hyderabad Area, India India
Profession
Verification Engineer at Xilinx
Secteur d’activité
Electronics / Computer Hardware
À propos
Functional Verification Engineer with experience in development of verification environment, testcases for module and system level verification. Experience in understanding and debugging verilog behavioral design.
Mots-clés
uvm bit bash register model
Tout plus