Prasenjit Dey

decoder multiplexer memory read and memory write. hardware implementation of memory transfer e.g. hardware implementation of bus transfer using mult register transfer language c++ graphics programming c graphics programming codeblocks baseline network benes network omega network delta network banyan network multistage interconnection network bus based interconnection networks switch based interconnection networks single stage interconnection network crossbar network multiple bus interconnection network single bus interconnection network auc curve roc curve false negetive false positive true negetive true positive confussion matrix recall precision specificity metric sensitivity metric accuracy metric classification in machine learning crop yield prediction using linear regression mathematical concepts of linear regression model crop yield prediction in python crop yield prediction concepts of linear regression concepts of regression problem regression problem clustering classification problem cross validation test data validation data training data lebels&features of data unlebelled data lebelled data reinforced learning unsupervised learning supervised learning learning algorithms of machine learning facts about human brain machine learning concepts use of machine learning in agriculture machine learning strategies in agriculture machine learning for crop yield prediction machine learning challenges in agriculture machine leanring in agriculture components of machine learning agricultural demand gamma parameter c parameter the kernel functions svm parameters maximum classification margin support vector machine (svm) nonlinear separability linear separability mal(minimum average latency) mal greedy cycles simple cycles state diagram reservation table dynamic pipeline general pipeline nonlinear pipeline response time execution time cpu time cpi clock rate clock frequency clock cycle amdahl's law assembly code for loop operations different types of registers in mips instruction set architecture assembly code for swap operation assembly code for if else operations j-format instructions instruction set i-format instructions r-format instructions counting algorithm thrashing opt page replacement lru page replacement fifo page replacement stack addressing mode relative addressing mode register indirect addressing mode register addressing mode inherent addressing mode indirect addressing mode indexed addressing mode implied addressing mode immediate addressing mode displacement addressing mode direct addressing mode auto-index addressing mode auto-increment addressing mode auto-decrement addressing mode addressing_modes #instruction encoding #implementing the nested subroutine calls by using #demonstrate branch instructions with a diagram. #different types of instructions in an instruction #instruction_length #demonstrate nested subroutine calls with a diagra #0-address instructions #1-address instructions #3-address instructions #instruction_cycle. #instruction_formats #2-address instructions #op-code encoding techniques #byte_ordering #instruction_set hardware implementation of memory unit using ram a magnetic disks rom chip ram chip split cache unified cache write back write through cache write policies temporal and spatial locality of references locality of references set-associative mapping fully-associative mapping direct mapping cache mapping non-restoring division algorithm restoring division algorithm booth's algorithm 1's & 2' complement excess-3 code gray code binary number system number systems instruction cycle different types of memory control unit arithmetic and logic unit cpu architecture