SlideShare une entreprise Scribd logo
1  sur  13
FPGA TECHNOLOGIES
AND FAMILIES
TOPICS
Introdu
ction
definitio
n
CONCLUSI
ON
TECHNOL
OGIES
FAMILIES
Introduction:

The full form of FPGA is “Field Programmable Gate Array”.
 It contains ten thousand to more than a million logic gates with
programmable interconnection.
Programmable interconnections are available for users or designers to
perform given functions easily.
A typical model FPGA chip is shown in the given figure.
There are I/O blocks, which are designed and numbered according to
function.
For each module of logic level composition, there are CLB’s (Configurable
Logic Blocks).
CLB performs the logic operation given to the module.
The inter connection between CLB and I/O blocks are made
with the help of horizontal routing channels, vertical routing
channels and PSM (Programmable Multiplexers).
The number of CLB it contains only decides the complexity of
FPGA.
The functionality of CLB’s and PSM are designed by VHDL or
any other hardware descriptive language. After programming,
CLB and PSM are placed on chip and connected with each
other with routing channels.
Definition:
A field-programmable gate array (FPGA) is an integrated
circuitdesigned to be configured by a customer or a designer after
manufacturing – hence the term "field-programmable".
 The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-
specific integrated circuit (ASIC).
Circuit diagrams were previously used to specify the configuration,
but this is increasingly rare due to the advent of electronic design
automation tools.
FPGAs contain an array of programmable logic blocks, and a
hierarchy of reconfigurable interconnects that allow the blocks to be
"wired together", like many logic gates that can be inter-wired in
different configurations.
 Logic blocks can be configured to perform complex combinational
functions, or merely simple logic gates like AND and XOR.
 In most FPGAs, logic blocks also include memory elements, which
may be simple flip-flops or more complete blocks of memory.[1]
 Many FPGAs can be reprogrammed to implement different logic
functions,[2] allowing flexible reconfigurable computing as performed
in computer software.
Technology:
• SRAM – based on static memory technology. In-system programmable
and re-programmable.
• Requires external boot devices. CMOS. Currently in use.
• Notably, flash memory or EEPROM devices may often load contents
into internal SRAM that controls routing and logic.
• Fuse – One-time programmable. Bipolar. Obsolete.
• Antifuse – One-time programmable. CMOS.
• PROM – Programmable Read-Only Memory technology. One-time
programmable because of plastic packaging. Obsolete.
• EPROM:Erasable Programmable Read-Only Memory technology. One-
time programmable but with window, can be erased with ultraviolet
(UV) light. CMOS. Obsolete.
• EEPROM – Electrically Erasable Programmable Read-Only Memory
technology. Can be erased, even in plastic packages. Some but not all
EEPROM devices can be in-system programmed. CMOS.
• Flash – Flash-erase EPROM technology. Can be erased, even in plastic
packages. Some but not all flash devices can be in-system
programmed. Usually, a flash cell is smaller than an equivalent
EEPROM cell and is therefore less expensive to manufacture. CMOS.
Conclusion:
An FPGA can be used to solve any problem which is computable.
This is trivially proven by the fact that FPGAs can be used to implement a soft microprocessor, such as
the Xilinx MicroBlaze or Altera Nios II.
Their advantage lies in that they are significantly faster for some applications because of their parallel nature and
optimality in terms of the number of gates used for certain processes
FPGAs have been reserved for specific vertical applications where the volume of production is small.
For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable
chip is more affordable than the development resources spent on creating an ASIC.
As of 2017, new cost and performance dynamics have broadened the range of viable applications.
FPGA TECHNOLOGY AND FAMILIES

Contenu connexe

Tendances

LOW POWER DESIGN VLSI
LOW POWER DESIGN VLSILOW POWER DESIGN VLSI
LOW POWER DESIGN VLSIDuronto riyad
 
Vlsi Summer training report pdf
Vlsi Summer training report pdfVlsi Summer training report pdf
Vlsi Summer training report pdfGirjeshVerma2
 
Digital VLSI Design : Introduction
Digital VLSI Design : IntroductionDigital VLSI Design : Introduction
Digital VLSI Design : IntroductionUsha Mehta
 
Physical design
Physical design Physical design
Physical design Mantra VLSI
 
Presentation on Industrial training in VLSI
Presentation on Industrial training in VLSI Presentation on Industrial training in VLSI
Presentation on Industrial training in VLSI NIT Raipur
 
Synchronous and asynchronous clock
Synchronous and asynchronous clockSynchronous and asynchronous clock
Synchronous and asynchronous clockNallapati Anindra
 
Low Power Design Approach in VLSI
Low Power Design Approach in VLSILow Power Design Approach in VLSI
Low Power Design Approach in VLSISilicon Mentor
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Field-programmable gate array
Field-programmable gate arrayField-programmable gate array
Field-programmable gate arrayPrinceArjun1999
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGAvelamakuri
 

Tendances (20)

CPLD xc9500
CPLD xc9500CPLD xc9500
CPLD xc9500
 
LOW POWER DESIGN VLSI
LOW POWER DESIGN VLSILOW POWER DESIGN VLSI
LOW POWER DESIGN VLSI
 
FPGA
FPGAFPGA
FPGA
 
Vlsi Summer training report pdf
Vlsi Summer training report pdfVlsi Summer training report pdf
Vlsi Summer training report pdf
 
Actel fpga
Actel fpgaActel fpga
Actel fpga
 
Digital VLSI Design : Introduction
Digital VLSI Design : IntroductionDigital VLSI Design : Introduction
Digital VLSI Design : Introduction
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
 
Physical design
Physical design Physical design
Physical design
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
 
Presentation on Industrial training in VLSI
Presentation on Industrial training in VLSI Presentation on Industrial training in VLSI
Presentation on Industrial training in VLSI
 
SRAM
SRAMSRAM
SRAM
 
Synchronous and asynchronous clock
Synchronous and asynchronous clockSynchronous and asynchronous clock
Synchronous and asynchronous clock
 
Low Power Design Approach in VLSI
Low Power Design Approach in VLSILow Power Design Approach in VLSI
Low Power Design Approach in VLSI
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing Techniques
 
VLSI routing
VLSI routingVLSI routing
VLSI routing
 
Low Power Techniques
Low Power TechniquesLow Power Techniques
Low Power Techniques
 
Rc delay modelling in vlsi
Rc delay modelling in vlsiRc delay modelling in vlsi
Rc delay modelling in vlsi
 
Field-programmable gate array
Field-programmable gate arrayField-programmable gate array
Field-programmable gate array
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGA
 
Introduction to FPGAs
Introduction to FPGAsIntroduction to FPGAs
Introduction to FPGAs
 

Similaire à FPGA TECHNOLOGY AND FAMILIES

Similaire à FPGA TECHNOLOGY AND FAMILIES (20)

Programmable Hardware - An Overview
Programmable Hardware - An OverviewProgrammable Hardware - An Overview
Programmable Hardware - An Overview
 
Fpga Knowledge
Fpga KnowledgeFpga Knowledge
Fpga Knowledge
 
Chapter 4
Chapter 4Chapter 4
Chapter 4
 
FIELD PROGRAMMABLE GATE ARRAYS AND THEIR APPLICATIONS
FIELD PROGRAMMABLE GATE ARRAYS AND THEIR APPLICATIONSFIELD PROGRAMMABLE GATE ARRAYS AND THEIR APPLICATIONS
FIELD PROGRAMMABLE GATE ARRAYS AND THEIR APPLICATIONS
 
Fpga lecture
Fpga lectureFpga lecture
Fpga lecture
 
FPGAs memory synchronization and performance evaluation using the open compu...
FPGAs memory synchronization and performance evaluation  using the open compu...FPGAs memory synchronization and performance evaluation  using the open compu...
FPGAs memory synchronization and performance evaluation using the open compu...
 
Fpga
FpgaFpga
Fpga
 
L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)
 
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).pptL12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
 
Subhadeep fpga-vs-mcu
Subhadeep fpga-vs-mcuSubhadeep fpga-vs-mcu
Subhadeep fpga-vs-mcu
 
FPGA Based VLSI Design
FPGA Based VLSI DesignFPGA Based VLSI Design
FPGA Based VLSI Design
 
UNIT-1.pptx
UNIT-1.pptxUNIT-1.pptx
UNIT-1.pptx
 
FPGA Embedded Design
FPGA Embedded DesignFPGA Embedded Design
FPGA Embedded Design
 
FPGA Introduction
FPGA IntroductionFPGA Introduction
FPGA Introduction
 
Selective fitting strategy based real time placement algorithm for dynamicall...
Selective fitting strategy based real time placement algorithm for dynamicall...Selective fitting strategy based real time placement algorithm for dynamicall...
Selective fitting strategy based real time placement algorithm for dynamicall...
 
System designing and modelling using fpga
System designing and modelling using fpgaSystem designing and modelling using fpga
System designing and modelling using fpga
 
14 284-291
14 284-29114 284-291
14 284-291
 
Cpld and fpga mod vi
Cpld and fpga   mod viCpld and fpga   mod vi
Cpld and fpga mod vi
 
91 94
91 9491 94
91 94
 
91 94
91 9491 94
91 94
 

Plus de revathilakshmi2

Teleportation presentation
Teleportation  presentationTeleportation  presentation
Teleportation presentationrevathilakshmi2
 
Agricultural destruction
Agricultural destructionAgricultural destruction
Agricultural destructionrevathilakshmi2
 
Revathi prasanna lakshmi.ch global warming
Revathi prasanna lakshmi.ch global warmingRevathi prasanna lakshmi.ch global warming
Revathi prasanna lakshmi.ch global warmingrevathilakshmi2
 
Efficient VLSI Architecture for Data Analysis of ECG
Efficient VLSI Architecture for Data Analysis of ECGEfficient VLSI Architecture for Data Analysis of ECG
Efficient VLSI Architecture for Data Analysis of ECGrevathilakshmi2
 

Plus de revathilakshmi2 (7)

Teleportation presentation
Teleportation  presentationTeleportation  presentation
Teleportation presentation
 
Vehicle rental app
Vehicle rental appVehicle rental app
Vehicle rental app
 
Agricultural destruction
Agricultural destructionAgricultural destruction
Agricultural destruction
 
Revathi prasanna lakshmi.ch global warming
Revathi prasanna lakshmi.ch global warmingRevathi prasanna lakshmi.ch global warming
Revathi prasanna lakshmi.ch global warming
 
Efficient VLSI Architecture for Data Analysis of ECG
Efficient VLSI Architecture for Data Analysis of ECGEfficient VLSI Architecture for Data Analysis of ECG
Efficient VLSI Architecture for Data Analysis of ECG
 
Agricultural robotics
Agricultural roboticsAgricultural robotics
Agricultural robotics
 
Presentation 3 1 1
Presentation 3 1 1Presentation 3 1 1
Presentation 3 1 1
 

Dernier

Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactdawncurless
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introductionMaksud Ahmed
 
The basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxThe basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxheathfieldcps1
 
1029 - Danh muc Sach Giao Khoa 10 . pdf
1029 -  Danh muc Sach Giao Khoa 10 . pdf1029 -  Danh muc Sach Giao Khoa 10 . pdf
1029 - Danh muc Sach Giao Khoa 10 . pdfQucHHunhnh
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfciinovamais
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Disha Kariya
 
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...Pooja Nehwal
 
Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3JemimahLaneBuaron
 
mini mental status format.docx
mini    mental       status     format.docxmini    mental       status     format.docx
mini mental status format.docxPoojaSen20
 
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...EduSkills OECD
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Krashi Coaching
 
The byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxThe byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxShobhayan Kirtania
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxiammrhaywood
 
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...anjaliyadav012327
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Celine George
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...fonyou31
 
Arihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfArihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfchloefrazer622
 
CARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxCARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxGaneshChakor2
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityGeoBlogs
 

Dernier (20)

Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introduction
 
The basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxThe basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptx
 
1029 - Danh muc Sach Giao Khoa 10 . pdf
1029 -  Danh muc Sach Giao Khoa 10 . pdf1029 -  Danh muc Sach Giao Khoa 10 . pdf
1029 - Danh muc Sach Giao Khoa 10 . pdf
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdf
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..
 
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
 
Mattingly "AI & Prompt Design: The Basics of Prompt Design"
Mattingly "AI & Prompt Design: The Basics of Prompt Design"Mattingly "AI & Prompt Design: The Basics of Prompt Design"
Mattingly "AI & Prompt Design: The Basics of Prompt Design"
 
Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3
 
mini mental status format.docx
mini    mental       status     format.docxmini    mental       status     format.docx
mini mental status format.docx
 
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
 
The byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxThe byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptx
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
 
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...
JAPAN: ORGANISATION OF PMDA, PHARMACEUTICAL LAWS & REGULATIONS, TYPES OF REGI...
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
 
Arihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfArihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdf
 
CARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxCARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptx
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activity
 

FPGA TECHNOLOGY AND FAMILIES

  • 3. Introduction:  The full form of FPGA is “Field Programmable Gate Array”.  It contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily. A typical model FPGA chip is shown in the given figure. There are I/O blocks, which are designed and numbered according to function. For each module of logic level composition, there are CLB’s (Configurable Logic Blocks).
  • 4. CLB performs the logic operation given to the module. The inter connection between CLB and I/O blocks are made with the help of horizontal routing channels, vertical routing channels and PSM (Programmable Multiplexers). The number of CLB it contains only decides the complexity of FPGA. The functionality of CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After programming, CLB and PSM are placed on chip and connected with each other with routing channels.
  • 5. Definition: A field-programmable gate array (FPGA) is an integrated circuitdesigned to be configured by a customer or a designer after manufacturing – hence the term "field-programmable".  The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application- specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.
  • 6. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations.  Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR.  In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.[1]  Many FPGAs can be reprogrammed to implement different logic functions,[2] allowing flexible reconfigurable computing as performed in computer software.
  • 7. Technology: • SRAM – based on static memory technology. In-system programmable and re-programmable. • Requires external boot devices. CMOS. Currently in use. • Notably, flash memory or EEPROM devices may often load contents into internal SRAM that controls routing and logic. • Fuse – One-time programmable. Bipolar. Obsolete. • Antifuse – One-time programmable. CMOS. • PROM – Programmable Read-Only Memory technology. One-time programmable because of plastic packaging. Obsolete.
  • 8. • EPROM:Erasable Programmable Read-Only Memory technology. One- time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete. • EEPROM – Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS. • Flash – Flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
  • 9.
  • 10.
  • 11.
  • 12. Conclusion: An FPGA can be used to solve any problem which is computable. This is trivially proven by the fact that FPGAs can be used to implement a soft microprocessor, such as the Xilinx MicroBlaze or Altera Nios II. Their advantage lies in that they are significantly faster for some applications because of their parallel nature and optimality in terms of the number of gates used for certain processes FPGAs have been reserved for specific vertical applications where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. As of 2017, new cost and performance dynamics have broadened the range of viable applications.