SlideShare une entreprise Scribd logo

Multipliers in VLSI

•Télécharger en tant que PPT, PDF•
•
Kiranmai Sony
Kiranmai Sony

its a presentation on multipliers..which shows various types and its usage

Technologie
1  sur  23
Sp09 CMPEN 411 L20 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 20: Multiplier Design [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Sp09 CMPEN 411 L20 S.2 Review: Basic Building Blocks  Datapath Execution units - Adder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders  Control Finite state machines (PLA, ROM, random logic)  Interconnect Switches, arbiters, buses  Memory Caches (SRAMs), TLBs, DRAMs, buffers
Sp09 CMPEN 411 L20 S.3 The Binary Multiplication x + Partial products Multiplicand Multiplier Result 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1
Sp09 CMPEN 411 L20 S.4 Multiply Operation  Multiplication is just a a lot of additions multiplicand multiplier partial product array double precision product N 2N N can be formed in parallel
Sp09 CMPEN 411 L20 S.5 Multiplication Approaches  Right shift and add Partial product array rows are accumulated from top to bottom on an N-bit adder - After each addition, right shift (by one bit) the accumulated partial product to align it with the next row to add Time for N bits Tserial_mult = O(NTadder) = O(N2 ) for a RCA  Making it faster Use a faster adder Use higher radix (e.g., base 4) multiplication – O(N/2 Tadder) - Use multiplier recoding to simplify multiple formation (booth) Form the partial product array in parallel and add it in parallel  Making it smaller (i.e., slower) Use serial-parallel mult Use an array multiplier - Very regular structure with only short wires to nearest neighbor cells. Thus, very simple and efficient layout in VLSI Can be easily and efficiently pipelined
Sp09 CMPEN 411 L20 S.6 Serial-parallel multiplier structure
Sp09 CMPEN 411 L20 S.7 The Array Multiplier Y0 Y1 X3 X2 X1 X0 X3 HA X2 FA X1 FA X0 HA Y2X3 FA X2 FA X1 FA X0 HA Z1 Z3Z6Z7 Z5 Z4 Y3X3 FA X2 FA X1 FA X0 HA
Sp09 CMPEN 411 L20 S.11 Booth multiplier  Encoding scheme to reduce number of stages in multiplication.  Performs two bits of multiplication at once—requires half the stages.  Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.
Sp09 CMPEN 411 L20 S.12 Booth encoding  Two’s-complement form of multiplier: y = -2n yn + 2n-1 yn-1 + 2n-2 yn-2 + ... (first bit is the sign bit) (example, y=18=010010 y= -18 = 101110 )  Rewrite using 2a = 2a+1 - 2a : y = 2n (yn-1-yn) + 2n-1 (yn-2 -yn-1) + 2n-2 (yn-3 -yn-2) + ...  Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
Sp09 CMPEN 411 L20 S.13 Booth actions yi yi-1 yi-2 increment 0 0 0 0 0 0 1 x 0 1 0 x 0 1 1 2x 1 0 0 -2x 1 0 1 -x 1 1 0 -x 1 1 1 0 y = 2n (yn-1-yn) + 2n-1 (yn-2 -yn-1) + 2n-2 (yn-3 -yn-2) + ...  Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
Sp09 CMPEN 411 L20 S.14 Booth example  x = 1001 (910), y = 0111 (710).  P0 = 00000000  y3y2y1=011 y1y0y-1=11(0)  y1y0y-1 = 110, P1 = P0 - (1001) = 11110111  x shift left for 2 bits to be 100100  y3y2y1 = 011, P2 = P1+ (10*100100) = 11110111+01001000 = 001111111 (6310)  An array multiplier needs N addtions, booth multiplier needs only N/2 additions
Sp09 CMPEN 411 L20 S.15 Review: A 64-bit Adder/Subtractor 1-bit FA S0 C0=Cin C1 1-bit FA S1 C2 1-bit FA S2 C3 C64=Cout 1-bit FA S63 C63 ...  Ripple Carry Adder (RCA) built out of 64 FAs  Subtraction – complement all subtrahend bits (xor gates) and set the low order carry-in  RCA  advantage: simple logic, so small (low cost)  disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption) A0 B0 A1 B1 A2 B2 A63 B63 add/subt
Sp09 CMPEN 411 L20 S.16 Booth structure
Sp09 CMPEN 411 L20 S.17 Wallace-Tree Multiplier 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Partial products First stage Bit position 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Second stage Final adder FA HA (a) (b) (c) (d)
Sp09 CMPEN 411 L20 S.18 Wallace-Tree Multiplier Partial products First stage Second stage Final adder FA FA FA HA HA FA x3y3 z7 z6 z5 z4 z3 z2 z1 z0 x3y2 x2y3 x1y1x3y0 x2y0 x0y1 x0y2 x2y2 x1y3 x1y2x3y1 x0y3 x1y0 x0y Full adder = (3,2) compressor
Sp09 CMPEN 411 L20 S.19 Making it Faster: Tree Multiplier Structure partial product array reduction tree fast carry propagate adder (CPA) P (product) mux + reduction tree (log N) + CPA (log N) Q (‘ier) D (‘icand) D D D 0 0 0 0 multiple forming circuits interconnect
Sp09 CMPEN 411 L20 S.20 (4,2) Counter  Built out of two (3,2) counters (just FA’s!) all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position) the internal carry output is fed to the next higher weight position (indicated by the ) (3,2) (3,2) Note: Two carry outs - one “internal” and one “external”
Sp09 CMPEN 411 L20 S.22 Tiling (4,2) Counters  Reduces columns four high to columns only two high Tiles with neighboring (4,2) counters Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2) (3,2) (3,2) (3,2) (3,2) (3,2)
Sp09 CMPEN 411 L20 S.24 4x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters  How would you lay it out? five (4,2) counters 5-bit CPA multiplicand multiplier 8-bit product
Sp09 CMPEN 411 L20 S.25 8x8 Partial Product Array Reduction ‘icand ‘ier partial product array reduced partial product array  Wallace tree multiplier two rows of nine (4,2) counters one row of thirteen (4,2) counters to a 13-bit fast CPA
Sp09 CMPEN 411 L20 S.26 An 8x8 Multiplier Layout  How should it be laid out? multiplicand multiplier thirteen (4,2) counters nine (4,2) counters nine (4,2) counters 13-bit CPA
Sp09 CMPEN 411 L20 S.32 Multipliers —Summary • Optimization Goals Different Vs Binary Adder • Once Again: Identify Critical Path • Other possible techniques - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION - Logarithmic versus Linear (Wallace Tree Mult)
Sp09 CMPEN 411 L20 S.33 Next Lecture and Reminders  Next lecture Shifters, decoders, and multiplexers - Reading assignment – Rabaey, et al, 11.5-11.6

Recommandé

Fpga architectures and applications
Fpga architectures and applicationsFpga architectures and applications
Fpga architectures and applicationsSudhanshu Janwadkar
 
FPGA
FPGAFPGA
FPGAsubin mathew
 
Shifters
ShiftersShifters
ShiftersRabindranath Tagore University, Bhopal
 
System On Chip
System On ChipSystem On Chip
System On Chipanishgoel
 
Pass Transistor Logic
Pass Transistor LogicPass Transistor Logic
Pass Transistor LogicSudhanshu Janwadkar
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flowRajendra Kumar
 
Pipelining approach
Pipelining approachPipelining approach
Pipelining approachGopinathD17
 
Design and development of carry select adder
Design and development of carry select adderDesign and development of carry select adder
Design and development of carry select adderABIN THOMAS
 

Recommandé

Fpga architectures and applications
Fpga architectures and applicationsFpga architectures and applications
Fpga architectures and applicationsSudhanshu Janwadkar
 
FPGA
FPGAFPGA
FPGAsubin mathew
 
Shifters
ShiftersShifters
ShiftersRabindranath Tagore University, Bhopal
 
System On Chip
System On ChipSystem On Chip
System On Chipanishgoel
 
Pass Transistor Logic
Pass Transistor LogicPass Transistor Logic
Pass Transistor LogicSudhanshu Janwadkar
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flowRajendra Kumar
 
Pipelining approach
Pipelining approachPipelining approach
Pipelining approachGopinathD17
 
Design and development of carry select adder
Design and development of carry select adderDesign and development of carry select adder
Design and development of carry select adderABIN THOMAS
 
Array multiplier
Array multiplierArray multiplier
Array multiplierMathew George
 
VLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVishal kakade
 
CMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURESCMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURESVaishaliVaishali14
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clockMantra VLSI
 
Actel fpga
Actel fpgaActel fpga
Actel fpgaAnish Gupta
 
Sequential cmos logic circuits
Sequential cmos logic circuitsSequential cmos logic circuits
Sequential cmos logic circuitsSakshi Bhargava
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1vamshi krishna
 
Interfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessorInterfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessorVikas Gupta
 
301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilog301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilogSrinivas Naidu
 
DIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFETDIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFETPraveen Kumar
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design pptAnil Yadav
 
Asic design flow
Asic design flowAsic design flow
Asic design flowyogeshwaran k
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
 
Windowing techniques of fir filter design
Windowing techniques of fir filter designWindowing techniques of fir filter design
Windowing techniques of fir filter designRohan Nagpal
 
Low power high_speed
Low power high_speedLow power high_speed
Low power high_speednanipandu
 
Analog to digital converters, adc
Analog to digital converters, adcAnalog to digital converters, adc
Analog to digital converters, adcSaumya Ranjan Behura
 
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGY
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGYVERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGY
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGYSeelam Vasavi Sai Viswanada Prabhu Deva Kumar
 
Dynamic logic circuits
Dynamic logic circuitsDynamic logic circuits
Dynamic logic circuitsKalyan Kumar Kalita
 
Mux based array mul ppt
Mux based array mul pptMux based array mul ppt
Mux based array mul pptBhamidipati Gayatri
 
Bit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBhargavKatkam
 

Contenu connexe

Tendances

VLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVishal kakade
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clockMantra VLSI
 
Sequential cmos logic circuits
Sequential cmos logic circuitsSequential cmos logic circuits
Sequential cmos logic circuitsSakshi Bhargava
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1vamshi krishna
 
Interfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessorInterfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessorVikas Gupta
 
301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilog301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilogSrinivas Naidu
 
DIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFETDIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFETPraveen Kumar
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design pptAnil Yadav
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
 
Windowing techniques of fir filter design
Windowing techniques of fir filter designWindowing techniques of fir filter design
Windowing techniques of fir filter designRohan Nagpal
 
Low power high_speed
Low power high_speedLow power high_speed
Low power high_speednanipandu
 

Tendances (20)

Array multiplier
Array multiplierArray multiplier
Array multiplier
 
VLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVLSI subsystem design processes and illustration
VLSI subsystem design processes and illustration
 
CMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURESCMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURES
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clock
 
Actel fpga
Actel fpgaActel fpga
Actel fpga
 
Sequential cmos logic circuits
Sequential cmos logic circuitsSequential cmos logic circuits
Sequential cmos logic circuits
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing Techniques
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1
 
Interfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessorInterfacing memory with 8086 microprocessor
Interfacing memory with 8086 microprocessor
 
301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilog301378156 design-of-sram-in-verilog
301378156 design-of-sram-in-verilog
 
DIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFETDIFFERENTIAL AMPLIFIER using MOSFET
DIFFERENTIAL AMPLIFIER using MOSFET
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design ppt
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
 
Windowing techniques of fir filter design
Windowing techniques of fir filter designWindowing techniques of fir filter design
Windowing techniques of fir filter design
 
Low power high_speed
Low power high_speedLow power high_speed
Low power high_speed
 
Analog to digital converters, adc
Analog to digital converters, adcAnalog to digital converters, adc
Analog to digital converters, adc
 
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGY
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGYVERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGY
VERY LARGE SCALE INTEGRATION (VLSI) TECHNOLOGY
 
Dynamic logic circuits
Dynamic logic circuitsDynamic logic circuits
Dynamic logic circuits
 

En vedette

Bit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBhargavKatkam
 
The Multipliers Seminar
The Multipliers SeminarThe Multipliers Seminar
The Multipliers SeminarGreg McKeown
 
All VLSI programs
All VLSI programsAll VLSI programs
All VLSI programsGouthaman V
 

En vedette (6)

Mux based array mul ppt
Mux based array mul pptMux based array mul ppt
Mux based array mul ppt
 
Bit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBit Serial multiplier using Verilog
Bit Serial multiplier using Verilog
 
The Multipliers Seminar
The Multipliers SeminarThe Multipliers Seminar
The Multipliers Seminar
 
VERILOG CODE
VERILOG CODEVERILOG CODE
VERILOG CODE
 
All VLSI programs
All VLSI programsAll VLSI programs
All VLSI programs
 
Booth Multiplier
Booth MultiplierBooth Multiplier
Booth Multiplier
 

Similaire à Multipliers in VLSI

ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGICANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGICSupanna Shirguppe
 
Hardware combinational
Hardware combinationalHardware combinational
Hardware combinationalDefri Tan
 
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...Hsien-Hsin Sean Lee, Ph.D.
 
Opampless sigma delta_2019
Opampless sigma delta_2019Opampless sigma delta_2019
Opampless sigma delta_2019takashi miki
 
Instruction_Set.pdf
Instruction_Set.pdfInstruction_Set.pdf
Instruction_Set.pdfboukomra
 
Lesson 8_et438b (2).ppsx
Lesson 8_et438b (2).ppsxLesson 8_et438b (2).ppsx
Lesson 8_et438b (2).ppsxBkannan2
 
Bt0064 logic design1
Bt0064 logic design1Bt0064 logic design1
Bt0064 logic design1Techglyphs
 
Logic Design - Chapter 5: Part1 Combinattional Logic
Logic Design - Chapter 5: Part1 Combinattional LogicLogic Design - Chapter 5: Part1 Combinattional Logic
Logic Design - Chapter 5: Part1 Combinattional LogicGouda Mando
 
Design of Counter Using SRAM
Design of Counter Using SRAMDesign of Counter Using SRAM
Design of Counter Using SRAMIOSRJECE
 
Ceng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer AdderCeng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer Addergueste731a4
 
A Simple Communication System Design Lab #4 with MATLAB Simulink
A Simple Communication System Design Lab #4 with MATLAB SimulinkA Simple Communication System Design Lab #4 with MATLAB Simulink
A Simple Communication System Design Lab #4 with MATLAB SimulinkJaewook. Kang
 
fyp....fyp.....fyp.....
fyp....fyp.....fyp.....fyp....fyp.....fyp.....
fyp....fyp.....fyp.....VisualBee.com
 
Admission in india 2015
Admission in india 2015Admission in india 2015
Admission in india 2015Edhole.com
 
Programmable array-logic-and-programmable-logic-array
Programmable array-logic-and-programmable-logic-arrayProgrammable array-logic-and-programmable-logic-array
Programmable array-logic-and-programmable-logic-arrayJher Carlson Atasan
 
Digital electronics Multiplexers & Demultiplexers
Digital electronics Multiplexers & DemultiplexersDigital electronics Multiplexers & Demultiplexers
Digital electronics Multiplexers & DemultiplexersSweta Kumari Barnwal
 

Similaire à Multipliers in VLSI (20)

ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGICANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
 
Hardware combinational
Hardware combinationalHardware combinational
Hardware combinational
 
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...
Lec5 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Branch Pred...
 
Chapter-04.pdf
Chapter-04.pdfChapter-04.pdf
Chapter-04.pdf
 
Opampless sigma delta_2019
Opampless sigma delta_2019Opampless sigma delta_2019
Opampless sigma delta_2019
 
Instruction set
Instruction setInstruction set
Instruction set
 
Instruction_Set.pdf
Instruction_Set.pdfInstruction_Set.pdf
Instruction_Set.pdf
 
Lesson 8_et438b (2).ppsx
Lesson 8_et438b (2).ppsxLesson 8_et438b (2).ppsx
Lesson 8_et438b (2).ppsx
 
Bt0064 logic design1
Bt0064 logic design1Bt0064 logic design1
Bt0064 logic design1
 
Logic Design - Chapter 5: Part1 Combinattional Logic
Logic Design - Chapter 5: Part1 Combinattional LogicLogic Design - Chapter 5: Part1 Combinattional Logic
Logic Design - Chapter 5: Part1 Combinattional Logic
 
13486500-FFT.ppt
13486500-FFT.ppt13486500-FFT.ppt
13486500-FFT.ppt
 
Design of Counter Using SRAM
Design of Counter Using SRAMDesign of Counter Using SRAM
Design of Counter Using SRAM
 
Ofdm.pptx
Ofdm.pptxOfdm.pptx
Ofdm.pptx
 
Ceng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer AdderCeng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer Adder
 
A Simple Communication System Design Lab #4 with MATLAB Simulink
A Simple Communication System Design Lab #4 with MATLAB SimulinkA Simple Communication System Design Lab #4 with MATLAB Simulink
A Simple Communication System Design Lab #4 with MATLAB Simulink
 
fyp....fyp.....fyp.....
fyp....fyp.....fyp.....fyp....fyp.....fyp.....
fyp....fyp.....fyp.....
 
Admission in india 2015
Admission in india 2015Admission in india 2015
Admission in india 2015
 
Programmable array-logic-and-programmable-logic-array
Programmable array-logic-and-programmable-logic-arrayProgrammable array-logic-and-programmable-logic-array
Programmable array-logic-and-programmable-logic-array
 
pandu-vivek (1)
pandu-vivek (1)pandu-vivek (1)
pandu-vivek (1)
 
Digital electronics Multiplexers & Demultiplexers
Digital electronics Multiplexers & DemultiplexersDigital electronics Multiplexers & Demultiplexers
Digital electronics Multiplexers & Demultiplexers
 

Dernier

Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)Zilliz
 
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...apidays
 
Six Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal OntologySix Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal Ontologyjohnbeverley2021
 
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...Orbitshub
 
Artificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyArtificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyKhushali Kathiriya
 
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ..."I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...Zilliz
 
Corporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxCorporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxRustici Software
 
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...apidays
 
Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfsudhanshuwaghmare1
 
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Angeliki Cooney
 
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMECloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMESafe Software
 
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...apidays
 
Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...apidays
 
Elevate Developer Efficiency & build GenAI Application with Amazon Q​
Elevate Developer Efficiency & build GenAI Application with Amazon Q​Elevate Developer Efficiency & build GenAI Application with Amazon Q​
Elevate Developer Efficiency & build GenAI Application with Amazon Q​Bhuvaneswari Subramani
 
CNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In PakistanCNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In Pakistandanishmna97
 
DEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
DEV meet-up UiPath Document Understanding May 7 2024 AmsterdamDEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
DEV meet-up UiPath Document Understanding May 7 2024 AmsterdamUiPathCommunity
 
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Victor Rentea
 
WSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2
 
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMECloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMESafe Software
 

Dernier (20)

+971581248768>> SAFE AND ORIGINAL ABORTION PILLS FOR SALE IN DUBAI AND ABUDHA...
+971581248768>> SAFE AND ORIGINAL ABORTION PILLS FOR SALE IN DUBAI AND ABUDHA...+971581248768>> SAFE AND ORIGINAL ABORTION PILLS FOR SALE IN DUBAI AND ABUDHA...
+971581248768>> SAFE AND ORIGINAL ABORTION PILLS FOR SALE IN DUBAI AND ABUDHA...
 
Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)
 
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
 
Six Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal OntologySix Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal Ontology
 
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...
Navigating the Deluge_ Dubai Floods and the Resilience of Dubai International...
 
Artificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyArtificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : Uncertainty
 
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ..."I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
 
Corporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxCorporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptx
 
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...
Apidays New York 2024 - Passkeys: Developing APIs to enable passwordless auth...
 
Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdf
 
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
 
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMECloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
 
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
 
Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...
 
Elevate Developer Efficiency & build GenAI Application with Amazon Q​
Elevate Developer Efficiency & build GenAI Application with Amazon Q​Elevate Developer Efficiency & build GenAI Application with Amazon Q​
Elevate Developer Efficiency & build GenAI Application with Amazon Q​
 
CNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In PakistanCNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In Pakistan
 
DEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
DEV meet-up UiPath Document Understanding May 7 2024 AmsterdamDEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
DEV meet-up UiPath Document Understanding May 7 2024 Amsterdam
 
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
 
WSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering Developers
 
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FMECloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
 

Multipliers in VLSI

  • 1. Sp09 CMPEN 411 L20 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 20: Multiplier Design [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
  • 2. Sp09 CMPEN 411 L20 S.2 Review: Basic Building Blocks  Datapath Execution units - Adder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders  Control Finite state machines (PLA, ROM, random logic)  Interconnect Switches, arbiters, buses  Memory Caches (SRAMs), TLBs, DRAMs, buffers
  • 3. Sp09 CMPEN 411 L20 S.3 The Binary Multiplication x + Partial products Multiplicand Multiplier Result 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1
  • 4. Sp09 CMPEN 411 L20 S.4 Multiply Operation  Multiplication is just a a lot of additions multiplicand multiplier partial product array double precision product N 2N N can be formed in parallel
  • 5. Sp09 CMPEN 411 L20 S.5 Multiplication Approaches  Right shift and add Partial product array rows are accumulated from top to bottom on an N-bit adder - After each addition, right shift (by one bit) the accumulated partial product to align it with the next row to add Time for N bits Tserial_mult = O(NTadder) = O(N2 ) for a RCA  Making it faster Use a faster adder Use higher radix (e.g., base 4) multiplication – O(N/2 Tadder) - Use multiplier recoding to simplify multiple formation (booth) Form the partial product array in parallel and add it in parallel  Making it smaller (i.e., slower) Use serial-parallel mult Use an array multiplier - Very regular structure with only short wires to nearest neighbor cells. Thus, very simple and efficient layout in VLSI Can be easily and efficiently pipelined
  • 6. Sp09 CMPEN 411 L20 S.6 Serial-parallel multiplier structure
  • 7. Sp09 CMPEN 411 L20 S.7 The Array Multiplier Y0 Y1 X3 X2 X1 X0 X3 HA X2 FA X1 FA X0 HA Y2X3 FA X2 FA X1 FA X0 HA Z1 Z3Z6Z7 Z5 Z4 Y3X3 FA X2 FA X1 FA X0 HA
  • 8. Sp09 CMPEN 411 L20 S.11 Booth multiplier  Encoding scheme to reduce number of stages in multiplication.  Performs two bits of multiplication at once—requires half the stages.  Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.
  • 9. Sp09 CMPEN 411 L20 S.12 Booth encoding  Two’s-complement form of multiplier: y = -2n yn + 2n-1 yn-1 + 2n-2 yn-2 + ... (first bit is the sign bit) (example, y=18=010010 y= -18 = 101110 )  Rewrite using 2a = 2a+1 - 2a : y = 2n (yn-1-yn) + 2n-1 (yn-2 -yn-1) + 2n-2 (yn-3 -yn-2) + ...  Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
  • 10. Sp09 CMPEN 411 L20 S.13 Booth actions yi yi-1 yi-2 increment 0 0 0 0 0 0 1 x 0 1 0 x 0 1 1 2x 1 0 0 -2x 1 0 1 -x 1 1 0 -x 1 1 1 0 y = 2n (yn-1-yn) + 2n-1 (yn-2 -yn-1) + 2n-2 (yn-3 -yn-2) + ...  Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
  • 11. Sp09 CMPEN 411 L20 S.14 Booth example  x = 1001 (910), y = 0111 (710).  P0 = 00000000  y3y2y1=011 y1y0y-1=11(0)  y1y0y-1 = 110, P1 = P0 - (1001) = 11110111  x shift left for 2 bits to be 100100  y3y2y1 = 011, P2 = P1+ (10*100100) = 11110111+01001000 = 001111111 (6310)  An array multiplier needs N addtions, booth multiplier needs only N/2 additions
  • 12. Sp09 CMPEN 411 L20 S.15 Review: A 64-bit Adder/Subtractor 1-bit FA S0 C0=Cin C1 1-bit FA S1 C2 1-bit FA S2 C3 C64=Cout 1-bit FA S63 C63 ...  Ripple Carry Adder (RCA) built out of 64 FAs  Subtraction – complement all subtrahend bits (xor gates) and set the low order carry-in  RCA  advantage: simple logic, so small (low cost)  disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption) A0 B0 A1 B1 A2 B2 A63 B63 add/subt
  • 13. Sp09 CMPEN 411 L20 S.16 Booth structure
  • 14. Sp09 CMPEN 411 L20 S.17 Wallace-Tree Multiplier 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Partial products First stage Bit position 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Second stage Final adder FA HA (a) (b) (c) (d)
  • 15. Sp09 CMPEN 411 L20 S.18 Wallace-Tree Multiplier Partial products First stage Second stage Final adder FA FA FA HA HA FA x3y3 z7 z6 z5 z4 z3 z2 z1 z0 x3y2 x2y3 x1y1x3y0 x2y0 x0y1 x0y2 x2y2 x1y3 x1y2x3y1 x0y3 x1y0 x0y Full adder = (3,2) compressor
  • 16. Sp09 CMPEN 411 L20 S.19 Making it Faster: Tree Multiplier Structure partial product array reduction tree fast carry propagate adder (CPA) P (product) mux + reduction tree (log N) + CPA (log N) Q (‘ier) D (‘icand) D D D 0 0 0 0 multiple forming circuits interconnect
  • 17. Sp09 CMPEN 411 L20 S.20 (4,2) Counter  Built out of two (3,2) counters (just FA’s!) all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position) the internal carry output is fed to the next higher weight position (indicated by the ) (3,2) (3,2) Note: Two carry outs - one “internal” and one “external”
  • 18. Sp09 CMPEN 411 L20 S.22 Tiling (4,2) Counters  Reduces columns four high to columns only two high Tiles with neighboring (4,2) counters Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2) (3,2) (3,2) (3,2) (3,2) (3,2)
  • 19. Sp09 CMPEN 411 L20 S.24 4x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters  How would you lay it out? five (4,2) counters 5-bit CPA multiplicand multiplier 8-bit product
  • 20. Sp09 CMPEN 411 L20 S.25 8x8 Partial Product Array Reduction ‘icand ‘ier partial product array reduced partial product array  Wallace tree multiplier two rows of nine (4,2) counters one row of thirteen (4,2) counters to a 13-bit fast CPA
  • 21. Sp09 CMPEN 411 L20 S.26 An 8x8 Multiplier Layout  How should it be laid out? multiplicand multiplier thirteen (4,2) counters nine (4,2) counters nine (4,2) counters 13-bit CPA
  • 22. Sp09 CMPEN 411 L20 S.32 Multipliers —Summary • Optimization Goals Different Vs Binary Adder • Once Again: Identify Critical Path • Other possible techniques - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION - Logarithmic versus Linear (Wallace Tree Mult)
  • 23. Sp09 CMPEN 411 L20 S.33 Next Lecture and Reminders  Next lecture Shifters, decoders, and multiplexers - Reading assignment – Rabaey, et al, 11.5-11.6

Notes de l'éditeur

  1. Right shift approach (almost) always used because left shift requires 2n bit adder
  2. One simple,small way to implement is the serial-parallel multiplier. So called because the n-bit multiplier is fed in serially while the m bit multiplicand is held in parallel.
  3. See Wayne Wolf book the
  4. a balanced delay tree 2 csa delays total
  5. For class handout
  6. For lecture a balanced delay tree 2 csa delays total
  7. For class handout
  8. For lecture
  9. Completely populate (costs more in terms of (4,2) counters) – advantage is the CPA doesn’t have to be as wide, so the multiplier faster, and the reduction tree is more “regular”