Overview of AMD's Native Quad Core Microprocessor

1. AMD Quad Core Barcelona MPU
August 31, 2007
Don Scansen
Technology Analyst
Semiconductor Insights
dons@semiconductor.com

2. Barcelona Die – Close-up on Two 2
Cores
Core 1
Core 1 Core 2
Core 2

3. 3
Barcelona Architecture
L3 Cache
Core 1 Core 2
Northbridge
Core 3 Core 4
DDR2 /DDR3

4. 4
Processor Core Design
Instruction
Load and fetch and
128 bit store Code decode
FPU
execution
L1 data L1
cache L2 instruction
control cache
L2

5. 5
Quad Core Die Architecture
•AMD’s Advantage •Intel’s Advantage
– Native quad core – Intel set to launch
for faster CPU 45nm dual core
without scaling Penryn line
technology
– Intel will package
– Affordable solution
two dual cores
– Large L3 cache is
together as they
shared, optimizing
memory use do now to offer a
– Northbridge “quad” device
memory controller
on die

6. 6
AMD 65nm Transistor Structure
NFET
Tensile
stress liner Contact
Nickel
silicide
Poly
Sidewall gate
spacers
Channel

7. 7
Dislocation Defect
Dislocation between silicon
atomic planes

8. 8
SRAM Cache Design
L2 and L3 6T SRAM unit cell:
0.54µm X 1.47µm = 0.79µm2

9. AMD and Intel Head-to-Head 9
(before Penryn Launch)
AMD Barcelona Native Intel Quad Core
Quad Kentsfield
Core
Die Size 284mm2 284mm2 (142 X 2 die)
Cell Size 0.79 µm2 0.72µm2
Total Memory 4.5MB 8.25MB
Cache
Process 65nm SOI DSL, e-SiGe, 65nm Bulk DSL, e-SiGe,
11M Cu 8M Cu

10. 10
After Intel’s Penryn Launches
?

11. 11
What’s next?
• Will AMD’s success come down to core on die
versus core in package?
• When will Intel produce a quad die?
• Will Intel stay ahead by leveraging its
manufacturing prowess and packaging multiple
MPU dies within a single package?