VTU 3rd Semester E&C Department, Logic Design Unit 7 Detailed Notes

1. 12
ODD
SEMESTER
LOGIC
DESIGN-­‐3-­‐CLASS
NOTES
–
UNIT7
Shivoo
Koteshwar
Professor,
E&C
Department,
PESIT
SC
Sequential
Design
1
• Introduction
• Mealy
and
Moore
Models
• State
Machine
Notation
• Synchronous
Sequential
Circuit
Analysis
Reference
Books:
• Digital
Logic
Applications
and
Design”,
John
M
Yarbrough,
Thomson
Learning,
2001
• “Logic
and
computer
design
Fundamentals”,
Mono
and
Kim,
Pearson,
Second
edition,
2001
UNIT
7:
Sequential
Design
-­‐
I:
Introduction,
Mealy
and
Moore
Models,
State
Machine
Notation,
Synchronous
Sequential
Circuit
Analysis,
[(Text
book
1)
6.1,
6.2,
6.3]
6
Hours
P e o p l e s
E d u c a t i o n
S o c i e t y
S o u t h
C a m p u s
( w w w . p e s . e d u )

2. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Sequential Machine:
A sequential circuit is said to be a synchronous sequential circuit if it
satisfies the following conditions:
• There is at least one flip-flop in every loop
• All flip-flops have the same type of dynamic clock
• All clock inputs of all the flip-flops are driven by the same clock
signal
There are two versions of this model called the Mealy Model and the Moore
model. The only difference is in the way the output signals are generated.
• Mealy Model: Outputs depend on current state and inputs
• Moore Model: Outputs only depend on current state
Differences between Moore and Mealy Models:
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3. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
State Machine Notation:
Input Variable: All variables that originate outside the sequential machine
(SM)
Output Variable: All variables that exit the SM
State Variable: The output of memory (FF) defines the state of a SM.
Excitation Variable: Inputs to memory (FF)
State: The state of the SM is defined by the content of memory
Flip Flop
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4. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
IMPLEMENTING A STATE DIAGRAM USING J-K
FLIPFLOP
This is a 5-step process:
1. Understand the State Diagram
2. Write the State Table
3. Encode the states and rewrite the state table
4. Select FF to be used
a. Derive the excitation Table (Optional if you remember it)
b. Fill the excitation variable (Inputs for Flip-Flops)
c. Simplify using K-Maps
5. Write the schematic diagram
Step1: Understand the State Diagram
Looking at the state diagram, we notice that it’s a mealy model
implementation. The state diagram shows that there are 4 states (A, B, C
and D), 2 input variables (x and y) and one output (z)
Note: In the State table, PS = Present State & NS = Next State
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5. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step2: Write the State Table:
Step3: Encode the states and rewrite the state table
2n states are possible with n number of Flip Flops. So 4 states require 2 Flip-
Flops.
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6. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step4: Select FF to be used
As in this problem, we are supposed to implement using JK Flip-Flops, lets
follow these 3 steps:
a. Derive the excitation Table
b. Fill the excitation variable
c. Simplify using K-Maps
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Notes
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7. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step4(a): Deriving Excitation Table for J-K Flip-Flop
From the above, we can write the following table:
Expanding this we can write the table as below:
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Notes
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8. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
In the above table, we notice the following:
• For both J=0, K=0 and J=0, K=1, when Present state is 0, next state
is 0. This means, irrespective of value of K, when J=0 and Present
state is 0, the Next state will be 0 OR J=0, K=d, PS=0 => NS=0
• For both J=0, K=0 and J=1, K=0, when Present state is 1, next state
is 1. This mean, irrespective of value of J, when K=1 and Present
state is 1, the Next state will be 1 OR J=d, K=0, PS =1 => NS= 1
• For both J=0, K=1 and J=1, K=1, when Present state is 1, next state
is 0. This means irrespective of value of J, when K=0 and Present
state is 1, the Next state will be 0 OR J=d, K=0, PS=1 => NS=0
• For both J=1, K=1 and J=1, K=0, when Present state is 0, next state
is 1. This means, irrespective of value of K, when J=1 and Present
state is 0, the Next state will be 1 OR J=1, K=d, PS=0 => NS=1
We can re-write the table as below:
Step
4(b): Filling the Excitation Table (Inputs for Flip-Flops)
In the state table derived earlier, we have PS=FAFB (Outputs of the flip-
flops) and state variables (Next State). Now using these two and the
excitation table of J-K Flip-Flop, we need to derive the inputs or the
excitation of the 2 Flip-Flops to be used
For example, for row1, bit 1 (FA), to get Present State=0 and Next State=0,
we need JAKA=0d. Similarly fill the JAKA column using bit 1 of FAFB column
& NS column and JBKB column using bit 0 of FAFB column & NS column
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9. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
When we fill the entire table, we get the following:
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Notes
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10. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step
4(c): Simplify using K-Maps
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Koteshwar’s
Notes
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11. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step5: Write the Schematic Diagram
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Koteshwar’s
Notes
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12. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Synchronous Sequential Circuit Analysis
Design is a synthesis process to take pieces and put them together to form a
functional whole. Analysis, on the other hand, requires breaking the whole
into component pieces
• Synthesis process is easier then analysis because the designer’s
reasons for making a particular decision are clear
• Here we will start with a circuit and proceed to determine the state
table or state diagram
Analysis is a 6 step process
1. Understand the schematic diagram
2. Derive the equations for inputs of flip-flops (Excitation variables)
and outputs
3. Using the equation, fill the K-Maps
4. Write the State Table
a. Using K-Maps, fill the state table
b. Derive the excitation table for JK Flip-Flop (Optional if you
remember it)
c. Fill the state variable (Next State)
5. Decode the states and rewrite the state table
6. Write the State Diagram
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Koteshwar’s
Notes
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13. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step1: Understand the Schematic Diagram
Looking at the schematic diagram, we notice that it’s implemented using JK
Flip-Flops. The schematic shows that there are 2 Flip-Flops so possible
states would be 4 – A, B, C and D. We also notice that there are 2 inputs x
and y and one input, z.
Step2: Derive the equations for inputs of flip-flops (Excitation
variables) and outputs
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Notes
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14. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step3: Using the equation, fill the K-Maps
Step4: Write the State Table
This is a 3 step process:
a. Using K-Maps, fill the state table
b. Derive the excitation table for JK Flip-Flop (Optional if you
remember it)
c. Fill the state variable (Next State)
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Koteshwar’s
Notes
14
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15. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step4(a): Using K-Maps, fill the State Table
Step4(b): Deriving Excitation Table for J-K Flip-Flop
From the above, we can write the following table:
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Koteshwar’s
Notes
15
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16. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Expanding this we can write the table as below:
In the above table, we notice the following:
• For both J=0, K=0 and J=0, K=1, when Present state is 0, next state
is 0. This means, irrespective of value of K, when J=0 and Present
state is 0, the Next state will be 0 OR J=0, K=d, PS=0 => NS=0
• For both J=0, K=0 and J=1, K=0, when Present state is 1, next state
is 1. This mean, irrespective of value of J, when K=1 and Present
state is 1, the Next state will be 1 OR J=d, K=0, PS =1 => NS= 1
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Koteshwar’s
Notes
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17. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
• For both J=0, K=1 and J=1, K=1, when Present state is 1, next state
is 0. This means irrespective of value of J, when K=0 and Present
state is 1, the Next state will be 0 OR J=d, K=0, PS=1 => NS=0
• For both J=1, K=1 and J=1, K=0, when Present state is 0, next state
is 1. This means, irrespective of value of K, when J=1 and Present
state is 0, the Next state will be 1 OR J=1, K=d, PS=0 => NS=1
We can re-write the table as below:
Step
4(c): Filling the State Variable (Next State)
In the state table derived earlier, we have PS=FAFB (Outputs of the flip-
flops) and inputs to Flip-Flops. Using these two and the excitation table of
J-K Flip-Flop, we need to derive the State variables (Next State)
For example, for row1, bit 1 (FA), with Present State=0 and JAKA=01, the
next state would be 0.
Similarly fill the NS bit1 column using bit 1 of FAFB column & JAKA column
and NS bit0 column using bit 0 of FAFB column & JBKB column.
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Koteshwar’s
Notes
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18. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
We get the following table:
Step
5: Decode the states and rewrite the state table
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Koteshwar’s
Notes
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19. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
In the above state table, we notice that in each state, all possible
combinations of inputs (xy) are covered i.e 4 possible combinations. You
can write the state diagram using the above table.
Optional: For ease of writing the state diagram, we can further try to reduce
the number of arcs from each state (circle) by studying the state table
e.g. In State A, irrespective of y, when x=0, it stays at A and when x=1, it
goes to B. So you can reduce from 4 arcs to 2 arcs, eliminate 2 arcs.
Similarly you can do the same at state B
So the final table looks like
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Notes
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20. Logic
Design
(3rd
Semester)
UNIT
7
Notes
v1.0
Step6: Write the state diagram
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Koteshwar’s
Notes
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