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[object Object],10  November 2008 Svetozar Jovanovic
On June 1991 I’ve got five years degree in Electronic/electrical Engineering, achieved at the University Politecnico di Milano with thesis about fault tolerant multiprocessor system, based on Motorola  68000  processors. Was a system running on a real time multitasking operating system kernel, custom written. The purpose was a digital protection relay, secure system for high voltage 50KV power transmission line protection against short circuits. Won prize " ERCOLE BOTTANI "  on  1990 , assigned to a best specializing branch student, for the last  three years  studies   Foreign Languages English: fluent  Italian: fluent French: basic Serbian-Croatian : middle Svetozar Jovanovic
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Svetozar Jovanovic
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Svetozar Jovanovic
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Svetozar Jovanovic
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],CASRAM ITALIANA /  RAIL  Svetozar Jovanovic
CASRAM ITALIANA / RAIL Here follows the image of digital speedmater: Svetozar Jovanovic
CASRAM ITALIANA /  RAIL  Here follows the image of maneuovre integrated bench: Svetozar Jovanovic
PHILIPS  SOUND & VISION (Belgium) in ITCL division (International technology centre of Leuven,  February 1999 until October 2000) HW Senior Consultant-Architect in consumer electronics for a SSA (Solid state Audio) project  Role,  objectives, summary: SSA MP3 Architecture build-up, market inspection for a system components. Design of developing/debug/test system platform for a SSA ASIC, based on Arm 720 RISC CPU, and fixed point DSP (for confidentiality reasons the name is unknown), integrated together on AMBA bus structure. Power consumption (hall effect sensors on PCB traces current) evaluation, benchmarking of different algorithms . Project responsible for developing and debug/test branch, in team with Philips Semiconductors.  Plan and organise and specs for integration activity in team  Subcontractors co-ordination. Svetozar Jovanovic
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],PHILIPS  SOUND & VISION Svetozar Jovanovic
Block Schematics SSA LFBGA208 Socket POWER JTAG/TCB USB PPI IIC CD Block AD/DA/RC GPIO UART IIS/SPDIF LCD MCI SM Tuner RD24K FLASH SDRAM SRAM Hardware Interface Optional Hardware Interface Optional Plug In Module REAL24 SAA7750 1V8 2V5 8V 5V 3V3 PHILIPS  SOUND & VISION Here follows the Solid state audio block diagram  Svetozar Jovanovic
MAGNETI MARELLI  (ITA,  1998- 1999) AUTOMOTIVE HW/System Senior Consultant in automotive for multifunctional car INFOCENTER, Lybra project:  Role summary,  objectives Development and design Graphic/control board 32 bit MIPS RISC processor based, for colour TFT 320 x 240 display imaging/messaging (up to 16 bit colour resolution), and interfaced with other car system components like navigation system, radio and car serial control link.  Thermal evaluations, mixed switching/linear power supply architecture, improving power consumption.  Electronic component selection and validation, and related problems (multiple sourcing, and replacing, cost, component life and availability) Preventive PCB layout architecture evaluation, and placement synthesis to obtain robust HW base from EMC and functional feasibility point of view, agreeing to mechanical/dimensional constraints.  Final HW architecture synthesis, accordingly to functional requirements and peripheral system constraint, and also with ”open” architecture, to minimise future revising impact.  HW/FW prototype start-up and low level FW/HW debug  Project Environment  summary Cadence tools for schematic entry and PCB layout, thermal simulation Compatibility to automotive thermal, electric norms, EMC and testing. Svetozar Jovanovic
MAGNETI  MARELLI Car  infocenter for  LYBRA  image: Svetozar Jovanovic
SOME  OTHER  CONSULTANCY EXPERIENCES: ALSTOM  RAILWAYS  ( SESTO S.GIOVANNI - MILAN  April 2005 – January 2007 ) Architect-Designer in the embedded ETHERNET rack module for the interface with external world C.S.I.I  ( MONZA) BANK SECURITY COMPANY ( December 2004 – March 2005) Architect and Senior Developer TCP/IP ETHERNET – 485 /232 bridge, integrated with a security Bank alarm system, to create a link between each agency and centralized watch place MARCONI – SELENIA,  NAVY  DEFENSE  SYSTEM (GENOVA  May 2003 – June 2004) Senior designer in the RX part of flying object, remote controlled over a unidirectional high frequency  link  with a TX  control console on ship board  (200 Km) operating range Svetozar Jovanovic
CONTACT  INFORMATIONS: E-mail  :  [email_address]   ,  [email_address] Mobile:  0039  338 239 49 93 Web-site: www.wireless-power.it Svetozar Jovanovic

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Powerp Sveto 2 Eng

  • 1.
  • 2. On June 1991 I’ve got five years degree in Electronic/electrical Engineering, achieved at the University Politecnico di Milano with thesis about fault tolerant multiprocessor system, based on Motorola 68000 processors. Was a system running on a real time multitasking operating system kernel, custom written. The purpose was a digital protection relay, secure system for high voltage 50KV power transmission line protection against short circuits. Won prize " ERCOLE BOTTANI " on 1990 , assigned to a best specializing branch student, for the last three years studies   Foreign Languages English: fluent Italian: fluent French: basic Serbian-Croatian : middle Svetozar Jovanovic
  • 3.
  • 4.
  • 5.
  • 6.
  • 7. CASRAM ITALIANA / RAIL Here follows the image of digital speedmater: Svetozar Jovanovic
  • 8. CASRAM ITALIANA / RAIL Here follows the image of maneuovre integrated bench: Svetozar Jovanovic
  • 9. PHILIPS SOUND & VISION (Belgium) in ITCL division (International technology centre of Leuven, February 1999 until October 2000) HW Senior Consultant-Architect in consumer electronics for a SSA (Solid state Audio) project Role, objectives, summary: SSA MP3 Architecture build-up, market inspection for a system components. Design of developing/debug/test system platform for a SSA ASIC, based on Arm 720 RISC CPU, and fixed point DSP (for confidentiality reasons the name is unknown), integrated together on AMBA bus structure. Power consumption (hall effect sensors on PCB traces current) evaluation, benchmarking of different algorithms . Project responsible for developing and debug/test branch, in team with Philips Semiconductors. Plan and organise and specs for integration activity in team Subcontractors co-ordination. Svetozar Jovanovic
  • 10.
  • 11. Block Schematics SSA LFBGA208 Socket POWER JTAG/TCB USB PPI IIC CD Block AD/DA/RC GPIO UART IIS/SPDIF LCD MCI SM Tuner RD24K FLASH SDRAM SRAM Hardware Interface Optional Hardware Interface Optional Plug In Module REAL24 SAA7750 1V8 2V5 8V 5V 3V3 PHILIPS SOUND & VISION Here follows the Solid state audio block diagram Svetozar Jovanovic
  • 12. MAGNETI MARELLI (ITA, 1998- 1999) AUTOMOTIVE HW/System Senior Consultant in automotive for multifunctional car INFOCENTER, Lybra project: Role summary, objectives Development and design Graphic/control board 32 bit MIPS RISC processor based, for colour TFT 320 x 240 display imaging/messaging (up to 16 bit colour resolution), and interfaced with other car system components like navigation system, radio and car serial control link. Thermal evaluations, mixed switching/linear power supply architecture, improving power consumption. Electronic component selection and validation, and related problems (multiple sourcing, and replacing, cost, component life and availability) Preventive PCB layout architecture evaluation, and placement synthesis to obtain robust HW base from EMC and functional feasibility point of view, agreeing to mechanical/dimensional constraints. Final HW architecture synthesis, accordingly to functional requirements and peripheral system constraint, and also with ”open” architecture, to minimise future revising impact. HW/FW prototype start-up and low level FW/HW debug Project Environment summary Cadence tools for schematic entry and PCB layout, thermal simulation Compatibility to automotive thermal, electric norms, EMC and testing. Svetozar Jovanovic
  • 13. MAGNETI MARELLI Car infocenter for LYBRA image: Svetozar Jovanovic
  • 14. SOME OTHER CONSULTANCY EXPERIENCES: ALSTOM RAILWAYS ( SESTO S.GIOVANNI - MILAN April 2005 – January 2007 ) Architect-Designer in the embedded ETHERNET rack module for the interface with external world C.S.I.I ( MONZA) BANK SECURITY COMPANY ( December 2004 – March 2005) Architect and Senior Developer TCP/IP ETHERNET – 485 /232 bridge, integrated with a security Bank alarm system, to create a link between each agency and centralized watch place MARCONI – SELENIA, NAVY DEFENSE SYSTEM (GENOVA May 2003 – June 2004) Senior designer in the RX part of flying object, remote controlled over a unidirectional high frequency link with a TX control console on ship board (200 Km) operating range Svetozar Jovanovic
  • 15. CONTACT INFORMATIONS: E-mail : [email_address] , [email_address] Mobile: 0039 338 239 49 93 Web-site: www.wireless-power.it Svetozar Jovanovic