2. Ils permettent de modifier l’état d’un signal ou de signaux
suivant le résultat d’un test ou d’une condition. En logique
combinatoire ils sont souvent utilisés avec les instructions :
- when … else …
- with …. Select ….
Opérateurs relationnels
3. Les instructions du mode « concurrent ».
Affectation conditionnelle : when .........else
Cette instruction modifie l’état d’un signal suivant le résultat d’une condition logique
entre un ou des signaux, valeurs, constantes.
SIGNAL <= valeur when condition else autre valeur when autre
condition;
Exemple N°1 :
-- S1 prend la
valeur de E2 quand E1=’1’ sinon S1 prend
la -- valeur ‘0’
S1 <= E2 when ( E1= ‘1’) else ‘0’;
Schéma correspondant :
Library ieee;
Use ieee.std_logic_1164.all;
entity test is
port (
E1,E2 : in std_logic;
S1:out std_logic
);
end test;
architecture DESCRIPTION of test is
begin
S1 <= E2 when ( E1= '1') else '0';
end DESCRIPTION;
4. Library ieee;
Use ieee.std_logic_1164.all;
entity lab1 is
port (
E1,E2 : in std_logic;
S1:out std_logic
);
end lab1;
architecture DESCRIPTION of
lab1 is
begin
S1 <= E2 when ( E1 < '1') else
'0';
end DESCRIPTION
Opérateurs relationnels
5. Entré
A2 A1 A0 S1 S0
0 0 1 1 1
1 0 0 0 1
1 0 1 1 0
Les instructions du mode « concurrent ».
Affectation conditionnelle : when .........else
Cette instruction modifie l’état d’un signal suivant le résultat d’une condition logique entre un ou des
signaux, valeurs, constantes.
SIGNAL <= valeur when condition else autre valeur when autre condition;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity table is
port(
A:in std_logic_vector(2 downto 0);
S: out std_logic_vector(1 downto 0)
);
End table;
architecture comporte of table is
Begin
S<="11"when A="001"else
"01"when A="100"else
"10"when A="101"else
"00" ;
end comporte ;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity porte is
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
S : out STD_LOGIC_VECTOR(1 downto 0)
);
end porte;
architecture bhv of porte is
begin
S(0) <= (A(0) and (not A(1) and not A(2))) or ((not A(0)) and
(A(1) and A(2)));
S(1) <= (A(0) and (not A(1) and not A(2))) or ((not A(0)) and
(A(1) and A(2)));
end bhv;
6. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity additionneur1bit is
port(
B: in std_logic;
A: in std_logic_vector(1 downto 0) ;
S: out std_logic_vector(1 downto 0)
);
end additionneur1bit;
architecture comporte of
additionneur1bit is
Signal BA std_logic_vector(2 downto 0);
begin
BA<= B & A ;
S <= "11" when BA ="001"
else "01" when BA ="100"
else "10" when BA ="101"
else "00" ;
end comporte ;
When ..else
Cas des signaux d’entres de types différents
A partir de table de vérité
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity porte is
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
S : out STD_LOGIC_VECTOR(1 downto 0)
);
end porte;
architecture bhv of porte is
begin
S(0) <= (A(0) and (not A(1) and not A(2))) or ((not
A(0)) and (A(1) and A(2)));
S(1) <= (A(0) and (not A(1) and not A(2))) or ((not
A(0)) and (A(1) and A(2)));
end bhv;
7. Les instructions du mode « concurrent ».
Affectation conditionnelle : when .........else
Cette instruction modifie l’état d’un signal suivant le résultat d’une condition logique entre un ou des
signaux, valeurs, constantes.
SIGNAL <= valeur when condition else autre valeur when autre condition;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lab1 is
port(
D0,D1 : in std_logic;
SEL: in std_logic;
S : out std_logic
);
End lab1;
architecture comporte of lab1 is
Begin
S <= D0 when (SEL= '0') else
D1 when (SEL= '1') ;
end comporte ;
Multiplexeur 2 VERS 1
8. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MUX is
port(
D0,D1,D2,D3 : in std_logic;
SEL: in std_logic_vector(1 downto 0);
S : out std_logic
);
end MUX;
architecture comporte of MUX is
begin
S………………….
Multiplexeur 4 VERS 1
9. Entré
A2 A1 A0 S1 S0
0 0 1 1 1
1 0 0 0 1
1 0 1 1 0
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity table is
port(
A:in std_logic_vector(2 downto 0);
S: out std_logic_vector(1 downto 0)
);
End table;
architecture comporte of table is
Begin
with A select
S <= "11" when "001",
"01" when "100",
"10" when "101",
"00" when others;
end comporte ;
Les instructions du mode « concurrent ».
Affectation Sélective : with ……. select
Cette instruction permet d’affecter différentes valeurs à un signal, selon les valeurs prises par un signal dit de
sélection
.with SIGNAL_DE_SELECTION select SIGNAL <= expression when valeur_de_selection,
[expression when valeur_de_selection,]
[expression when others];
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity table is
port(
A:in std_logic_vector(2 downto 0);
S: out std_logic_vector(1 downto 0)
);
End table;
architecture comporte of table is
Begin
S<="11"when A="001"else
"01"when A="100"else
"10"when A="101"else
"00" ;
end comporte ;
10. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity porte is
port(
A:in std_logic_vector(1 downto 0);
B:in std_logic;
S: out std_logic_vector(1 downto 0)
);
End porte;
architecture comporte of porte is
BA : std_logic_vector(0 to 2)
Begin
BA <= B & A;
with BA select
S <= "11" when "001",
"01" when "100",
"10" when "101",
"00" when others;
end comporte ;
With ..select
Cas des signaux d’entres de types différents
12. library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity porte is
port (
………………………………
);
end porte;
architecture comporte of porte is
Begin
………………….
Wen else
13. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity porte is
port (
……………………………..
);
end porte;
architecture comporte of porte is
begin
………………………………..;
end comporte;
with select
14. Multiplexeur 2 VERS 1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MUX is
port( D0,D1 , SEL : in std_logic;
S : out std_logic );
end MUX;
architecture comporte of MUX is
Begin
with SEL select
S <= D0 when '0',
D1 when '1',
'0' when others;
end comporte ;
Remarque: when others est nécessaire
car il faut toujours définir les autres cas du signal de
sélection pour prendre en compte toutes les valeurs
possibles de celui-ci. Schéma correspondant après
synthèse:
Les instructions du mode « concurrent ».
Affectation Sélective :
with SIGNAL_DE_SELECTION select SIGNAL <= expression when
valeur_de_selection, [expression when valeur_de_selection,]
[expression when others];
15. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity porte is
port(
…………………………
);
end porte;
architecture comporte of porte is
Begin
…………………………………….
end comporte ;
Affectation Sélective
16. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity porte is
port(
D0,D1,D2,D3 : in std_logic;
SEL: in std_logic_vector(1 downto 0);
S : out std_logic
);
end porte;
architecture comporte of porte is
Begin
with SEL select
S <= D0 when "00",
D1 when "01",
'0' when others;
-- Pour les autres cas de SEL S2
-- prendra la valeur 0 logique
end comporte ;
Exemple 2: Affectation sélective avec les autres cas forcés à ‘0’.
17. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity porte is
port(
D0,D1,D2,D3 : in std_logic;
SEL: in std_logic_vector(1 downto 0);
S : out std_logic
);
end porte;
architecture comporte of porte is
Begin
with SEL select
S <= D0 when "00",
D1 when "01",
'1' when others;
-- Pour les autres cas de SEL S2
-- prendra la valeur 1 logique
end comporte ;
Exemple 2: Affectation sélective avec les autres cas forcés à ‘1’.
18. library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lab1 is
port(
D0,D1,D2,D3 : in std_logic;
SEL: in std_logic_vector(1 downto 0);
S : out std_logic
);
end lab1;
architecture comlab1 of lab1 is
Begin
with SEL select
S <= D0 when "00",
D1 when "01",
'-' when others;
-- Pour les autres cas de SEL S2
-- prendre une valeur X quelconque
end comlab1 ;
Exemple 2: Affectation sélective avec les autres cas forcés à ‘-’.
19. library ieee;
use ieee.std_logic_1164.all;
entity PORTE is
port(
A:in std_logic_vector(3 downto 0);
SEL:in std_logic_vector(1 downto 0);
D0,D1,D2,D3:out std_logic_vector(3 downto 0));
end PORTE;
architecture fonction of PORTE is
begin
D0 <= A when (SEL="00") else "0000";
D1 <= A when (SEL ="01") else "0000";
D2 <= A when (SEL ="10") else "0000";
D3 <= A when (SEL ="11") else "0000";
end fonction;
Démultiplexeur when ..else
20. library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
entity circuit is
port(
A:in std_logic_vector(3 downto 0);
SEL:in std_logic_vector(1 downto 0);
D0,D1,D2,D3:out std_logic_vector(3
downto 0)
);
end circuit;
architecture Arch_circuit of circuit is
begin
with S select
D<= A & "000" when "11",
…………………………………………………
end Arch_circuit;
Démultiplexeur
with……select
21. library ieee;
use ieee.std_logic_1164.all;
entity Comparateur is
port(
a,b : in std_logic;
a_sup_b, a_inf_b, a_eq_b : out
std_logic);
end Comparateur;
architecture archConc of Comparateur
is
begin
a_sup_b <= '1' when a > b else '0';
a_inf_b <= '1' when a < b else '0';
a_eq_b <= '1' when a = b else '0';
end archConc;
Comparateur when……else
22. library ieee;
use ieee.std_logic_1164.all;
entity Comparateur is
port(
a,b : in std_logic;
a_sup_b, a_inf_b, a_eq_b : out
std_logic);
end Comparateur;
architecture archConc of Comparateur
is
begin
………………………………….
end archConc;
Comparateur with……select
23. library ieee;
use ieee.std_logic_1164.all;
entity porte is
port (
a, b : in std_logic;
a_sup_b, a_inf_b, a_eq_b : out std_logic
);
end porte;
architecture archConc of porte is
signal ab : std_logic_vector(1 downto 0); -- Concatenation of a and b
begin
ab <= a & b; -- Concatenate signals a and b
with ab select
a_sup_b <= '1' when "01",
'0' when others;
with ab select
a_inf_b <= '1' when "10",
'0' when others;
with ab select
a_eq_b <= '1' when "00" | "11",
'0' when others;
end architecture archConc;
Comparateur with……select
24. library ieee ;
use ieee.std_logic_1164.all;
entity dec2to4 is
port(
x : in std_logic_vector(1 downto 0);
En : in std_logic;
y : out std_logic_vector(3 downto 0)
);
end dec2to4;
architecture circuit_behavior of dec2to4 is
signal Enx : std_logic_vector(2 downto 0);
begin
Enx <= En& x;
with Enx select
y <= "0001 " when “100”;
“0010” when “101”;
“0100” when “110”;
“1000” when “111”
“0000” when others;
end circuit_behavior;
Décodeur With… select
25. library ieee ;
use ieee.std_logic_1164.all;
entity dec2to4 is
port(
…………………………………………..
);
end dec2to4;
architecture circuit_behavior of dec2to4 is
signal Enx : std_logic_vector(2 downto 0);
begin
…………………………………………..
end circuit_behavior;
Décodeur When .else
28. library ieee;use ieee.std_logic_1164.all;
entity exp3 is
port(
s_in : in std_logic;
s_out: out std_logic
);
end exp3;
architecture fonction of exp3 is
begin
process(s_in)
variable v1,v2,v3,v4:std_logic;
begin
v1:=not s_in;
v2:=s_in;
v3:=v1 and v2;
v4:=(v1 and v3) or s_in;
s_out<= not v4;
end process;
end fonction;
32. library IEEE;
use IEEE.std_logic_1164.all;
entity porte is
port (
D0, D1 : in std_logic;
sel : in std_logic;
x : out std_logic
);
end porte;
architecture arch_lab1 of porte is
begin
process (sel)
begin
if sel = '0' then
x <= D0;
elsif sel = '1' then
x <= D1;
else
x <= '0';
end if;
end process;
end arch_lab1;
33. library IEEE;
use IEEE.std_logic_1164.all;
entity porte is
port (
D0, D1, D2, D3 : in std_logic;
sel : in …………………
x : out std_logic
);
end porte;
architecture arch_lab1 of porte is
Begin
……………………………
end arch_lab1;
34. library ieee;
use ieee.std_logic_1164.all;
entity porte is
port (
D0, D1 : in std_logic;
sel : in std_logic;
x : out std_logic
);
end porte;
architecture arch_lab1 of porte is
begin
process (sel)
begin
case sel is
when '0' =>
x <= D0;
when '1' =>
x <= D1;
when others =>
x <= '0';
end case;
end process;
end arch_lab1;
35. library IEEE;
use IEEE.std_logic_1164.all;
entity porte is
port (
D0, D1, D2, D3 : in std_logic;
sel : ……………………..
x : out std_logic
);
end porte;
architecture arch_lab1 of porte is
Begin
……………………………
end arch_lab1;
36. Entré Sortie
A2 A1 A0 S1 S0
0 0 1 1 1
1 0 0 0 1
1 0 1 1 0
Donner une description avec
if..else
Case …i s
39. Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity add_select is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC;
sel : inout std_logic_vector(2 downto 0)
);
end add_select;
architecture comportementale of add_select is
begin
sel<=a&b&cin;
process(sel)
begin
case sel is
when ("000")=> sum<='0';cout<='0';
when "001" | "010" | "100"=> sum<='1';cout<='0';
when "101" | "110" | "011" => sum<='0';cout<='1';
when others =>sum <='1'; cout<='1';
end case;
end process;
end comportementale;
39
40. 40
Remarque: Le nom du process, mais il peut
être très utile pour repérer un process
parmi d’autres lors de phases de mise
au point ou de simulations.
43. 43
library ieee ;
use ieee.std_logic_1164.all;
entity polytech is
port(
bcd : in std_logic_vector(3 downto 0);
led_seg : out std_logic_vector(1 to 7));
end polytech;
architecture circuit_behavior of polytech is
begin
process (bcd)
begin
case bcd is
when "0000" => led_seg <= "1111110";
when "0001" => led_seg <= "0110000";
when "0010" => led_seg <= "1101101";
when "0011" => led_seg <= "1111001";
when "0100" => led_seg <= "0110011";
when "0101" => led_seg <= "1011011";
when "0110" => led_seg <= "1011111";
when "0111" => led_seg <= "1110000";
when "1000" => led_seg <= "1111111";
when "1001" => led_seg <= "1111011";
when others => led_seg <= "-------";
end case;
end process;
end circuit_behavior;
Exemple Afficheur sept segments
44. 44
Une description VHDL se compose de deux parties:
1. La description de l’interface Circuit (appelée Entity) avec le monde
qui l’utilise (connexions, brochages,…) celle-ci est constituée par la
liste des signaux de cette interface, leur sens et leur nature etc.
2. La description de la réalisation du circuit (appelée Architecture) qui
peut contenir quatre formes de descriptions:
1.Comportementale (Sans référence à des structures ou des
équations : table de vérité)
2. Temporelle ou flot des données (c’est à dire réaliser à partir des
équations booléennes )
3.Structurelle (c’est à dire réaliser à partir des composants
prédéfinis)
4. Mixte (c’est à dire réaliser à partir des composants prédéfinis et
des équations booléennes)
Différentes Approches de Description en VHDL
45. 45
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity lab1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end lab1;
architecture comportementale of lab1 is
begin
process(a,b,cin)
begin
if (A ='0' and B='0' and Cin='0' ) then Sum<='0';Cout<='0';
elsif (A ='0' and B='0' and Cin='1' ) then Sum<='1';Cout<='0';
elsif (A ='0' and B='1' and Cin='0' ) then Sum<='1';Cout<='0';
elsif (A ='0' and B='1' and Cin='1' ) then Sum<='0';Cout<='1';
elsif (A ='1' and B='0' and Cin='0' ) then Sum<='1';Cout<='0';
elsif (A ='1' and B='0' and Cin='1' ) then Sum<='0';Cout<='1';
elsif (A ='1' and B='1' and Cin='0' ) then Sum<='0';Cout<='1';
else Sum<='1';Cout<='1';
end if;
end process;
end comportementale;
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Additionneur
Complet
1 Bit
A
B
Cin
S
Cout
Modèle comportemental:
46. Modèle Flot des données : temporelle
46
Additionneur
Complet
1 Bit
A
S
B
Cin
équations booléennes
Comment faire?
AB
Cin
00 01 11 10
0 0 1 0 1
1 1 0 1 0
AB
Cin
00 01 11 10
0 0 0 1 0
1 0 1 1 1
S
Cout
S = A ⊕ B ⊕ Cin Cout=(A.B) + Cin (A
⊕B)
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
47. Modèle Flot des données : temporelle
47
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Additionneur_FD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end Additionneur_FD;
architecture Behavioral of Additionneur_FD is
Begin
S<= A xor B xor Cin;
Cout<= (A and B) or (Cin and (A xor B));
end Behavioral;
Additionneur
Complet
1 Bit
A
B
Cin
S
Cout
S = A ⊕ B ⊕ Cin
Cout=(A.B) + Cin (A
⊕B)
48. 48
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end lab1;
architecture Behavioral of lab1 is
Begin
S<= A xor B xor Cin;
Cout<= (A and B) or (Cin and (A xor B));
end Behavioral;
Additionneur
Complet
1 Bit
A
B
Cin
S
Cout
S = A ⊕ B ⊕ Cin
Cout=(A.B) + Cin (A
⊕B)
49. Description structurelle: composants
prédéfinis
• Un niveau de description peut faire appel à des
modules compilés indépendamment, et les
interconnecter de manière structurelle.
49
COMPONENT 1
COMPONENT 2
50. 50
Architecture structurelle :
Demi-adde
r
b
B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY additionneur IS
PORT (A,B: IN std_logic;
s,cout: OUT std_logic);
END additionneu;
ARCHITECTURE beh OF additionneu IS
begin
s <= A XOR B;
cout<= A AND B;
end beh;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY porteou IS
PORT(a,b: IN std_logic; c: OUT
std_logic);
END porteou;
ARCHITECTURE beh OF porteou IS
Begin
c <= a OR b;
end beh;
Cout
S
a
A
c
51. 51
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY structure IS
PORT(in1,in2,cin: IN std_logic;
sum,carry: OUT std_logic);
END structure;
ARCHITECTURE structural OF structure
is
COMPONENT additionneur
PORT (A,B: IN std_logic;
s,cout: OUT std_logic);
END COMPONENT;
COMPONENT porteou
PORT(a,b: IN std_logic;
c : OUT std_logic);
END COMPONENT;
SIGNAL s1,s2,s3 : std_logic;
BEGIN
H1 : additionneur PORT
MAP(A=>in1,B=>in2,Cout=>s1,s=>s2);
H2 : additionneur PORT
MAP(s2,B=>cin, s=>sum,Cout=>s3);
O1 : porteou PORT MAP(s1,s3,
carry);
END structural;
Demi-adde
r
B
Cout
S
A
a
b
c
52. 52
Architecture mixte :
Demi-adde
r
B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mixte IS
PORT (A,B: IN std_logic;
s,cout: OUT std_logic);
END mixte;
ARCHITECTURE beh OF mixte IS
begin
s <= A XOR B;
process(a,b)
begin
if(A='0' AND B='0')then cout<='0';
Elsif (A='1' AND B='0')then cout<='0';
Elsif (A='0' AND B='1')then cout<='0';
Else cout<='1';
end if;
end process;
end beh;
Cout
A