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A1 A2 1
V1
V2 VOUT
Cc
Differential
Input Stage
Second
Gain Stage
Output
Buffer
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A1
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signal signal
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Settling Time
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V2
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𝑆𝑖 =
𝑊𝑖
𝐿𝑖
𝑓𝑜𝑟 𝑡ℎ𝑒 𝑖𝑡ℎ 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟
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c
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42
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1  (min)1(max)03
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 )((max)1
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Design of two stage OP AMP

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Design of two stage OP AMP