VLSI

1. 2
Text Books:
• Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System Perspective, 2015, 4th
Edition, Pearson Education, Noida, India.
• http://emicroelectronics.free.fr/onlineCourses/VLSI/toc.html
(Design of VLSI Systems, Yusuf Leblebici)
Reference Books:
• Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits: Analysis and
Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.

2. IntegratedCircuit-Moore’sLaw
• Moore's law (In year 1975) is the observation that the number of transistors in an integrated
circuit (IC) doubles about every two years.
• Moore's law is an observation/empirical relationship and projection of a historical trend,
rather than a law of physics.
• The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor
and former CEO of the Intel (Integrated Electronics).
• The level of integration as measured by the number of logic gates in a monolithic chip has
been steadily rising for almost three decades.
Evolution of logic complexity in integrated circuits

3. • Less area/volume and therefore, compactness
• Less power consumption
• Less testing requirements at system level
• Higher reliability, mainly due to improved on-chip interconnects
• Higher speed, due to significantly reduced interconnection length
• Significant cost savings
IntegratedCircuit–DesignObjectives/Performancemetrics

4. VLSIDesignFlow-DesignPartitioning
Flowchart of VLSI design flow
Front end design (Involves gate
level HDL-EDA tools)
Back end design (Involves
transistor level CAD tools)
Architectural Design: User’s
perspective, what does it do?
Example: Instruction set, registers
MIPS, x86, Alpha,
PIC, ARM, …
Functional Design
Example: Single cycle, multcycle,
pipelined, superscalar?
Logic: how are functional blocks
constructed
Example: Ripple carry, carry
lookahead, carry select adders
Circuit: how are transistors used
Example: Complementary
CMOS, pass transistors, domino

5. 5
VLSIDesignFlow
• The design process, at various levels, is usually evolutionary in nature.
• It starts with a given set of requirements. Initial design is developed and tested
against the requirements.
• When requirements are not met, the design has to be improved.
• If such improvement is either not possible or too costly, then the revision of
requirements and its impact analysis must be considered.

6. • The Y-chart (first introduced by D.
Gajski) shown in Figure illustrates a
design flow for most logic chips, using
design activities on three different axes
(domains) which resemble the letter Y.
• The Y-chart consists of three major
domains, namely:
• behavioral domain
• structural domain
• geometrical layout/Physical domain
VLSIDesignFlow::Y-chart

7. • Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighboring steps, and
occasionally even remotely separated pairs.
• Although top-down design flow provides an excellent design process control, in reality,
there is no truly unidirectional top-down design flow. Both top-down and bottom-up
approaches have to be combined.
VLSIDesignFlow

8. • The use of hierarchy, or “divide and
conquer” technique involves dividing a
module into sub- modules and then
repeating this operation on the sub-
modules until the complexity of the
smaller parts becomes manageable.
• This approach is very similar to the
software case where large programs are
split into smaller and smaller sections
until simple subroutines, with well-
defined functions and interfaces, can be
written.
• A hierarchy structure can be described
in each domain (shown in Y-chart)
separately.
VLSIDesignHierarchy

9. VLSIDesignHierarchy::Structuraldomainexample-
Decompositionofafour-bitaddercircuit

10. VLSIDesignHierarchy:: Conceptsof Regularity,ModularityandLocality
The VLSI design hierarchy mush take care/satisfy of the following concepts.
Regularity:
The hierarchical decomposition of a large system should result in not only simple, but also
similar blocks, as much as possible. Regularity usually reduces the number of different
modules that need to be designed and verified, at all levels of abstraction.
Modularity:
The various functional blocks which make up the larger system must have well-defined
functions and interfaces.
Locality:
Internal details remain at the local level. The concept of locality also ensures that
connections are mostly between neighboring modules, avoiding long-distance
connections as much as possible.

11. VLSIDesignStyles
• Standard IC
• Application specific IC (ASIC) : Following are the various ASIC Design Styles

12. VLSIDesignStyles::full-custom
In full-custom style, the designer has many degrees of freedom to optimize a circuit design:
• Adjust individual transistor dimensions (channel width, channel length, aspect ratio, etc.)
to satisfy:
• DC specifications (voltage levels, switching thresholds)
• Transient specifications (delay times, rise- and fall-times)
• Freely choose the most appropriate topology (placement and routing) for each circuit
block.
• Decide for the interconnection strategy between neighboring blocks.
• Decide for the global distribution of power, ground and clock.

13. VLSIDesignStyles::standardcell
Each standard cell is pre-designed,
with:
• Same cell height for all elements in
the library
• Horizontal PWR and GND lines at
the top and at the bottom
• Fixed pin locations (inputs and
outputs)
“Routing"
Between
the cells

14. VLSIDesignStyles::standardcell-Examples
Every standard cell
is pre-designed for
different channel
widths to facilitate
current drive
capability.

15. VLSIDesignStyles::FPGA
Field Programmable Gate Array (FPGA):
• Fully fabricated FPGA chips containing thousands of logic gates or even more, with
programmable interconnects, are available to users for their custom hardware programming
to realize desired functionality.
• This design style provides a means for fast prototyping and also for cost-effective chip
design, especially for low-volume applications.
• A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of
configurable logic blocks (CLBs), and programmable interconnect structures.
• The programming of the interconnects is implemented by programming of RAM cells
whose output terminals are connected to the gates of MOS pass transistors.

16. VLSIDesignStyles::FPGA-Example
General architecture of Xilinx FPGAs.