Personal Information
Entreprise/Lieu de travail
Bengaluru Area, India, Karnataka India
Profession
Technical Program Committee Member DVCon USA 2018 at DVCon USA 2018
Secteur d’activité
Electronics / Computer Hardware
Site Web
www.cvcblr.com/blog
À propos
A dynamic technical evangelist in the domain of VLSI design, based in Bangalore – India. My areas of interest are the advanced verification solutions and methodologies such as SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc.
As CTO @CVC (www.cvcblr.com) my job is to stream line all the technical deliverables, meeting customer expectations and defining roadmap for near future. I provide support to leading edge semiconductor design companies on their verification methodologies and challenges.
I have the right mix of both Design house and EDA industry and hence can appreciate the strengths and weaknesses of both.
In my previous employment with various des...
Mots-clés
systemverilog
asic
vlsi
verilog
eda
cvc vmm systemverilog verilog debug verdi novas
ovm
vmm
Tout plus
Présentations
(3)Documents
(1)Personal Information
Entreprise/Lieu de travail
Bengaluru Area, India, Karnataka India
Profession
Technical Program Committee Member DVCon USA 2018 at DVCon USA 2018
Secteur d’activité
Electronics / Computer Hardware
Site Web
www.cvcblr.com/blog
À propos
A dynamic technical evangelist in the domain of VLSI design, based in Bangalore – India. My areas of interest are the advanced verification solutions and methodologies such as SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc.
As CTO @CVC (www.cvcblr.com) my job is to stream line all the technical deliverables, meeting customer expectations and defining roadmap for near future. I provide support to leading edge semiconductor design companies on their verification methodologies and challenges.
I have the right mix of both Design house and EDA industry and hence can appreciate the strengths and weaknesses of both.
In my previous employment with various des...
Mots-clés
systemverilog
asic
vlsi
verilog
eda
cvc vmm systemverilog verilog debug verdi novas
ovm
vmm
Tout plus