Hardware Accelerated Software Defined Radio Using FPGA
Advanced 5G wireless infrastructure should support any-to-any connectivity between densely arranged smart objects that form the emerging paradigm known as the Internet of Everything (IoE). While traditional wireless networks enable communication between devices using a single technology, 5G networks will need to support seamless connectivity between heterogeneous wireless objects, and consequently enable the proliferation of IoE networks. To tackle the complexity and versatility of the future IoE networks, 5G has to guarantee optimal usage of both spectrum and energy resources and further support technology-agnostic connectivity between objects. This can be realized by combining intelligent network control with adaptive software-defined air interfaces. In order to achieve this, current radio technology paradigms like Cloud RAN and Software Defined Radio (SDR) utilize centralized baseband signal processing mainly performed in software. With traditional SDR platforms, composed of separate radio and host commodity computer units, computationally-intensive signal processing algorithms and high-throughput connectivity between processing units are hard to realize. In addition, significant power consumption and large form factor may preclude any real-life deployment of such systems. On the other hand, modern hybrid FPGA technology tightly couples a FPGA fabric with hard core CPU on a single chip. This provides opportunities for implementing air interfaces based on hardware/software co-processing, resulting in increased processing throughput, reduced form factor and power consumption, while at the same time preserving flexibility. This paper examines how hybrid FPGAs can be combined with novel ideas such as RF Network-on-Chip (RFNoC) and partial reconfiguration, to form a flexible and compact platform for implementing low-power adaptive air interfaces. The proposed platform merges software and hardware processing units of SDR systems on a single chip. Therefore, it can provide interfaces for on-the-fly composition and reconfiguration of software and hardware radio modules. The resulting system enables the abstraction of air interfaces, where each access technology is composed of a structured sequence of modular radio processing units.
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Hardware Accelerated Software Defined Radio Using FPGA
- 1. 1 Hardware Accelerated Software Defined Radio Tarik Kazaz (tarik.kazaz@intec.ugent.be) 07/09/2015
- 2. Overview Common SDR approach Propposed approach Hardware accelerated SDR Use case example
- 3. Common SDR approach Intensive signal processing is done in host PC No real time processing Significant power and space consumption (no portability) FPGA is seriously underutilized! USRP Host PC ?
- 4. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P IFFT P/S & add CP Pulse shaping DAC & RF Transmitter
- 5. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P IFFT P/S & add CP Pulse shaping Baseband processing DAC & RF
- 6. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P IFFT P/S & add CP Pulse shaping Baseband processing DAC & RF
- 7. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P IFFT P/S & add CP Pulse shaping Baseband processing DAC & RF
- 8. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P P/S & add CP Baseband processing DAC & RF IFFT Pulse shaping
- 9. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P P/S & add CP Baseband processing DAC & RF IFFT Pulse shaping
- 10. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P P/S & add CP Baseband processing DAC & RF IFFT Pulse shaping
- 11. Common SDR approach Coding & Interleaving QAM mapping Pilot Insertion & S/P P/S & add CP Baseband processing DAC & RF IFFT Pulse shaping ?
- 12. Proposed approach Coding & Interleaving QAM mapping Pilot Insertion & S/P P/S & add CP DAC & RF IFFT Pulse shaping
- 13. Hardware accelerated SDR platform on top of Zynq Xilinx Zynq Dual Core ARM Cortex A9 GNU Radio FPGA Accelerated Block Linux Kernel Device Driver ARM to FPGA Interface FPGA Accelerator FPGA Fabric ARM TFlow GnuRadio with HW acceleration capabilities GReasy ARM - FPGA shared memory separate control and data plane interfaces
- 14. Hardware accelerated SDR platform on top of Zynq This concept enables Offload of GnuRadio blocks to FPGA Frees up processor to perform other tasks
- 15. Hardware accelerated SDR platform on top of Zynq This concept enables Offload of GnuRadio blocks to FPGA Real time reconfigurability Frees up processor to perform other tasks Configuration Port or ICAP Configuration Port Full Bit File Partial Bit Files FunctionA1 FunctionB1 FunctionC1FunctionC2 FunctionB2 FunctionA2FunctionA3
- 16. Hardware accelerated SDR platform on top of Zynq This concept enables Offload of GnuRadio blocks to FPGA Whole SDR system should fit on one board Real time reconfigurability Frees processor to perform other tasks
- 17. Example Scenario Different applications – different wireless standards Our platform should support various existing and future emerging wireless technologies at same time IoT-CUBE HUB IoT-CUBE HUB Internet Repository of SDR library and HW ACC 802.11g device 802.11ac device 802.15.4 device BLE device 802.11ah xyz device Download SDR packages from cloud Wireless as a Service
- 18. First step Locally reconfiguring FPGA part of platform Changing 802.15.4 Tx with 802.11g Tx Bitstream for 802.11g is stored locally on SD memory card Sniffing simultaneously 802.11g and 802.15.4 packets to detect reconfiguration IoT-CUBE HUB SD memory card 802.11g device 802.15.4 device
Notes de l'éditeur
- Intensive signal processing is done in host PC, on processor, - We know that CPUs have sequential-general propose nature, because of that there is no guarantee that certain processing task could be completed on time (or better to say there is no real time processing) - As a result limited number of radios can be supported with traditional SDR platforms - Also this approach implies the usage of host PC, which consumes significant power and space and precludes deployment of such a system in real life In same time USRP with FPGA as main processing unit is used just as interface for simple down/up conversion to/from baseband towards IF and RF - FPGA which is typically good candidate for dedicated parallel processing is in practice underutilized
- This is block scheme typical OFDM transmitter
- Which contains several units in baseband processing chain
- Realization of such system in GnuRadio would assume that all baseband processing is done on HOST PC
- While USRP with FPGA as main processing unit is used just for simple up conversion of signal from baseband to (IF or RF) or vice versa
- But there are 2 algorithms or processing blocks in transmitter chain
- 1. which are computationally intensive compared to others: IFFT and pulse shaping filtering
- General proposed processor is not dedicated for parallel and real time processing - Implementation of those algorithms on general proposed processor can imply that they will be bottlenecks of system
- 1. In same time the FPGA is underutilized at all, while those algorithms could be implemented on it
- 1. Obviously some things are done wrong in common
- Such a platform could be formed on top of Zynq SoC as it contains ARM (as an CPU) processing unit and FPGA on a single chip. There are several tools that should be run on ARM to form SW part of platform - TFlow is tool used for bitstream construction, which places and routes parameterized pre-compiled modules into a FPGA bitstream, and does so in a few seconds time (at least based on paper) – similar like software-only flow - Standard GnuRadio library is extended with HW accelerated blocks - Those two SW components are forming SDR framework which is called Greasy, originally developing is started computational laboratory at Virginia Institute of Technology. 3. Between ARM and FPGA there 4 high throughput interfaces which are used as data plane interface for forwarding samples 4. Memory mapped interfaces are used as control plane interfaces for control of FPGA accelerators from GnuRadio
- 1. What this approach certainly enables is offloading of computationally intensive GnuRadio blocks to FPGA 2. This frees up processor to perform other tasks
- 1. With addition of Partial Reconfiguration this approach could enable even real time configurability (less then 10ms) 2. Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption.
- 1. Such a system should be able to fit on one small PCB board which would enable usage of SDR in real life scenarios
- Here we will show example usage of such a platform in real life scenario. In future there will be more and more devices which will use different wireless technologies for establishing connectivity Also every few years there is new wireless standard emerging In order to support connectivity of devices that are using various technologies there is need for development of some sort of upgradable IoT gateway (we can call it IoT-CUBE HUB) SW part of IoT-CUBE HUB should have ability to download new SDR packages from cloud and to reprogram both HW and SW radio parts on SoC. We can see this concept as Wireless as a Service)
- As a first step we plan to illustrate the switching between two technologies - ZigBee and Wifi Tx While bitstream for reconfiguration would be loaded on SD memory card, instead of downloading from remote repository