The IoT Academy Embedded Systems Training Basic Circuit Design Part3

1. THE IOT ACADEMY
EMBEDDED SYSTEMS
Circuit Design

2. Design Abstraction Levels
2
n+n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM

3. What is design?
 1. Specify the problem
 2. Explore top-level decomposition
 3. Discover relevant information from diverse sources
 4. Perform system analysis (where possible)
 5. Make assumptions, prioritise problems
 6. Perform detailed prototype design
 7. Evaluate prototype
 test assumptions
 identify problems & areas for further work
 8. Improve design
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4. Design is not linear
4
Specify
Top-level
InformationAnalysisAssumptions
Prototype
Evaluate
Improve
Top-down
Bottom-up
These activities are
inter-dependent and
concurrent

5. Putting it all together
 Not all elements of design are “open”.
 Some problems are closed, with specific constraints that
allow only one solution
 Use analysisto solveclosed problems, to simplify the
design space
 No-one tells you which bits of analysis to do!
 Design requires both analysisand creative exploration
5

6. Design Concept
Todesignany electricalcircuit, eitheranalog or digital,
engineersneed to be able to predictthevoltagesand currents
at all placeswithinthe circuit.
Linearcircuits, that is, circuits wherein theoutputsare linearly
dependent on the inputs, can be analyzedby hand using complex
analysis.
Simple nonlinearcircuitscan also be analyzedin thisway.
Specializedsoftwarehas been created toanalyzecircuits thatare
eithertoocomplicatedor too nonlineartoanalyzeby hand.
First try to find a steadystatesolutionwhereinall the nodes
conform to Kirchhoff'sCurrent Law and thevoltagesacross and
througheach elementof thecircuit conform to thevoltage/current
equationsgoverning thatelement.
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7. Design Metrics
 How to evaluate performance of a digital circuit
(gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function
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8. Terminology in Circuit Design
 Impedance Matching
 DC Bias
 Noise Margin
 Pull up Resister
 Pull Down Resistor
 Filters
 Loading effect
 Fan in
 Fan out
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9. Impedance Matching
 It’s simplydefined as theprocess of making one impedance
look like another.
 Frequently, it becomes necessary to match a load impedance to
thesource or internalimpedance of a driving source.
 The maximum power transfertheoremsays that to transferthe
maximum amount of power from a source to a load, theload
impedance should match thesource impedance. In thebasic
circuit, a source may be dc or ac, and its internalresistance(Ri)
or generatoroutput impedance (Zg) drives a load resistance
(RL) or impedance (ZL):: RL = Ri or ZL = Zg
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10. Impedance Matching (Applications)
Antenna impedance must equal the transmitter output impedance
to receive maximum power.
Transmission lines have a characteristic impedance (ZO)
that must match the load to ensure maximum power
transfer and withstand loss to standing waves.
10

11. Fan-Out
 Typically, theoutput of a logicgate is connectedto the input(s) of one
or more logicgates
 The fan-out is the number of gates thatare connected to theoutput
of the driving gate:
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Fan-out leads to increased capacitive load on the
driving gate, and therefore longer propagation delay
•The input capacitances of the driven gates sum, and must be
charged through the equivalent resistance of the driver

12. Effect of Capacitive Loading
 When an input signal of a logicgate is changed, there is a propagation
delay before the output of the logicgatechanges. This is due to
capacitive loading at the output.
12

13. Propagation Delay in Timing Diagrams
To simplify the drawing of timing diagrams, we can approximate
the signal transitionsto be abrupt (though in realitytheyare
exponential).
To further simplify timing analysis, wecan definethe
propagation delay as
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14. Examples of Propagation Delay
14

15. Reliability―
Noise in Digital Integrated Circuits
15
i(t)
Inductive coupling Capacitive coupling Power and ground
noise
v(t) VDD

16. DC Operation
Voltage Transfer Characteristic
16
V(x)
V(y)
V
OH
VOL
VM
V
OH
VOL
f
V(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)

17. Mapping between analog and digital signals
17
V
IL
V
IH
V
in
Slope = -1
Slope = -1
VOL
VOH
V
out
“ 0” V
OL
V
IL
V
IH
V
OH
Undefined
Region
“ 1”

18. Definition of Noise Margins
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Noise margin high
Noise margin low
V
IH
V
IL
Undefined
Region
"1"
"0"
V
OH
V
OL
NMH
NML
Gate Output Gate Input

19. Noise Budget
 Allocatesgross noise margin to expected sources of
noise
 Sources: supplynoise, cross talk, interference, offset
 Differentiate between fixed and proportional noise
sources
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20. Key Reliability Properties
 Absolute noise margin values are deceptive
 a floating node is more easily disturbed than a node
driven by a low impedance (in terms of voltage)
 Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
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21. Fan-in and Fan-out
21
N
Fan-out N Fan-in M
M

22. The Ideal Gate
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R i = 
R o = 0
Fanout = 
NMH = NML = VDD/2
g = 
V in
V out

23. Delay Definitions
23

24. Example
 Need to set bias voltage (Vb) input to
alphanumeric LCD display module.
 From LCD datasheet:
 LCD module supply is 5v
 Vb >0.5v, Vb < 3v
 Circuit must adjust Vb to an unknown correct valuein thisrange
 Thissets LCD contrast
 Ib < 10uA
 ILCD = 2mA (typical)
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Specify

25. Bias Adjust Circuit
25
Bias
Adjust
Circuit
LCD
Module
Vb
+5V
GND
Top-down

26. Design ideas
 Use voltageregulator IC?
 Need to read datasheets to see how to make adjustable over
required range
 Use Zener diode (last year’s circuit)
 Does not help since not variable
 Use potential divider (P.D.) with variableresistor
 Simplest solution if feasible
 Could combine P.D. and Zener for slightly better
stability
 (probably not worth it)
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Multiple viewpoints

27. Variable resistors
 Preset resistors have three terminals, with a fixed
resistance between the two ends and a sliderwhich can
move anywhere between the two ends.
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PR1
Information

28. Detailed circuit design using variable resistor
 This circuit will allow
Vb to be adjusted
between 0.5v & 2v
 What values R1, R3,
PR2?
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R1
PR2
R3
2v
0.5v
Vb
+5v
GND
Vx
Vy
Detailed design

29. Know your resistors
 22k resistor is not 22,000 ohms!
 22k resistor has specified tolerance (1%,2%,5%)
 2% tolerance:0.98*22,000< R < 1.02*22,000
 Variableresistorstypicallyhave tolerance10%
 Resistors have preferred values:
 Fixed resistorsavailable in E24 series and multiples
1,1.1,1.2,1.3,1.5,1.6,1.8,2.0,2.2,2.4,2.7,3.0,3.3,3.6,3.9,4.3,4.7,5.1,5.6,
6.2,6.8,7.5,8.2,9.1
 Variableresistorsonly available: 1, 2, 5 and multiples!
 Check catalogues and datasheets
 Design for available precision & values
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Information

30. Analysis (ohms law)
 R3 = 0.5/(2-0.5)PR2
 R1 = (5-2.5)/(2-0.5)PR2
 Choose PR2 first, calculate R3,R1
 How accurate do these ratios need to be?
 If Vx>2V, Vy<0.5V the adjustment range includes the required
range of 0.5-2V
 Precision not required
 R3,R1 can be smaller then calculated
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Analysis

31. Assumptions
 PR2 too low => more current used in circuit.
 Assume want current as small as possible
 PR2 too high => Vb will vary too much with LCD bias
current change.
 Datasheet does not say how much bias current
changes so assume 10uA is possible (worst case,
since we know it is < 10uA)
 Datasheet does not say how accurate Vb must be:
assume 10%.
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Assumptions

32. Analysis
Approximateanalysis
Assume Thevenin equivalent resistance at Vy =
R3 (actually slightly smaller)
Assume OK at all other voltages if OK at Vy
50mV > R3.Ib = R3.10uA => R3 < 5k
=> total divider current = 1mA
Not too bad, but significant compared with ILCD
R1=50k, PR2=15k, R3=5k
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More analysis +
approximation

33. Are values realistic?
Variableresistorsareavailable10k,20k,50k
15k not possible
Couldscale by 2/3
R1=33k, PR2=10k, R3=3k3
Theseresistorvaluesare all available
Thisis notgood idea. Designing preciselyto limitsisdangerous.
Reduce R1, R3 by 20% toensure coverageof entirerangeeven if
resistorvaluesvary
R1=27k, PR2=10k, R3=2k7 (use E24 values)
Notethat precise values don’t matter
R1=22k, PR2=10k,R3=2k2 would also be fine
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Detailed
design

34. Optimise circuit
 Why bother with R1, R3?
 Not really needed, but allows better adjustment
 Resolution = minimum change in resistance value that a
variable resistor can be adjusted to.
 Typically 1%. 1.5V across PR2 =>15mV res
 R3 missing => 2V across PR2 => 20mV res
 R1 & R3 missing => 5V across PR2 => 50mV res
 R3 probablynot needed (1.5V -> 2V)
 R1 maybe also not needed (1.5V -> 5V)
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Optimise

35. Possible circuits
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R1
PR2
R3
2v
0.5v
Vb
+5v
GND
R1
PR2
Vb
+5v
GND
PR2
Vb
+5v
GND
10k
30k
3k0
20k
27k
50k
Guess which one is
recommended in the
LCD datasheets?

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