MPHS RC Prj

M etodologie di P rogettazine H ardware e S oftware Reconfigurable Computing - Projects -

EARENDIL ,[object Object],[object Object],[object Object],[object Object]

Earendil Design Flow: Basic Principles ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Earendil Design Flow: an Overview DRESD - HLR DRESD - BE

DRESD Project examples ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Motivations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Aims ,[object Object],[object Object],[object Object],[object Object],[object Object]

Core Generation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Core Generation ,[object Object],[object Object],[object Object],[object Object]

YaRA: the embedded 1D approach

YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa CLB x CLB y Layer

How to extend YaRA and Acheronte ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

D-ICAP: DRESD - ICAP ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

BiRF: Bitstream Relocation Filter ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],IP-Core Generator Tool

EDK System Creator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

BUBA ,[object Object],[object Object],[object Object],[object Object],[object Object]

ComIC ,[object Object],[object Object],[object Object],[object Object],[object Object]

ADG: Automatic Driver Generator ,[object Object],[object Object],[object Object]

BAnMaT: Bitstream Analizer Manipulator Tool ,[object Object],[object Object],[object Object],[object Object],[object Object]

Linux and reconfiguration software architecture

R econfiguration O f T he F PGA with L inux ,[object Object],[object Object],[object Object],[object Object]

L oad O n L inux ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Microlinux structure Kernel Source RamDisk image zImage.elf zImage.initrd.elf U-Boot & Bitstream Deployment on the board

Microlinux on Xilinx Virtex II Pro Virtex II Pro S D R A M F L A S H Driver Kernel APs MicroLinux boot image copy load boot contiene Absolute physical addresses

Development framework and compilation chain Xilinx Platform Studio Xparameters.h ./genMicroLinux Kernel Image ,[object Object],[object Object],[object Object],eMdev :

SyCERS - Objectives ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

TLM e SystemC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port

The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

A reconfigurable component using SystemC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],*g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex

Reconfigurable component behavior

DRESD online ,[object Object],[object Object],[object Object]

MPHS RC Prj

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