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Power Reduction Techniques

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Rajesh M
Rajesh M

Power Reduction Techniques at a glance

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Low power design techniques - Dynamic power - Reduce toggle count - RTL clock gating - Chip level, Unit level, Block level clock gating - Inferred clock gating using ICGs -- increase clock gating percentage - Reduce voltage - Multiple Modes for use cases - Structural placement (reducing interconnect cap) - Accurate power estimation to target re-architecting dynamic power critical blocks - Reduce cell drive strengths - Reduce total std_cell area - VT sweep to achieve best subset of cells for timing closure and lower power - dont_use/dont_touch settings - Reduce glitches/noise - Reduce total net length - Clustered placement, reduce detours - Multiple modes (different Vdd, different Frequency) - split rails (VDD_mem, VDD_logic correspondingly) - Relax max_trans constraint - compromise between design robustness and over-sizing of cells - Disable high drive strength cells if timing is met - Disable complex cells - Enable Register Retiming - Pin-swapping to offload high switching nets - Useful clock skew to lower the drive strength of cells in data path - Proper Technology node selection for your design - Multiple Voltage Islands - Low power designware (DW) datapath components - Achieve best Clock tree quality (latency, skew) - Results in less hold buffers, design area - Accurate timing constraints - Not to optimize some false or relaxed paths by design - Better PLL for jitter margins - Third party IPs - Multibit flip-flops to reduce clock tree power - Custom placement - SAIF based placement, Low Power Placement (LPP) flow - Best Memory placement, Floorplanning - which affects placement, total net length - Software scheduling to avoid peak power use cases - SRAM selection - Sweep to change floorplan and reduce total net length - Low Power Flop (LP Flops) usage in Synthesis
- Leakage power - Multi VT, multi drive strengths - Leakage, area recovery using ECOs - Power gating (header/footer) - Body bias - overdrive technique - Control LVT usage in PD (allow only % of LVT cells) - 3-sigma versus 2-sigma corners - Reduces yield but better leakage - Characterized library at power corner (Scaling factors across corners will be pessimistic)

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Power Reduction Techniques

  • 1. Low power design techniques - Dynamic power - Reduce toggle count - RTL clock gating - Chip level, Unit level, Block level clock gating - Inferred clock gating using ICGs -- increase clock gating percentage - Reduce voltage - Multiple Modes for use cases - Structural placement (reducing interconnect cap) - Accurate power estimation to target re-architecting dynamic power critical blocks - Reduce cell drive strengths - Reduce total std_cell area - VT sweep to achieve best subset of cells for timing closure and lower power - dont_use/dont_touch settings - Reduce glitches/noise - Reduce total net length - Clustered placement, reduce detours - Multiple modes (different Vdd, different Frequency) - split rails (VDD_mem, VDD_logic correspondingly) - Relax max_trans constraint - compromise between design robustness and over-sizing of cells - Disable high drive strength cells if timing is met - Disable complex cells - Enable Register Retiming - Pin-swapping to offload high switching nets - Useful clock skew to lower the drive strength of cells in data path - Proper Technology node selection for your design - Multiple Voltage Islands - Low power designware (DW) datapath components - Achieve best Clock tree quality (latency, skew) - Results in less hold buffers, design area - Accurate timing constraints - Not to optimize some false or relaxed paths by design - Better PLL for jitter margins - Third party IPs - Multibit flip-flops to reduce clock tree power - Custom placement - SAIF based placement, Low Power Placement (LPP) flow - Best Memory placement, Floorplanning - which affects placement, total net length - Software scheduling to avoid peak power use cases - SRAM selection - Sweep to change floorplan and reduce total net length - Low Power Flop (LP Flops) usage in Synthesis
  • 2. - Leakage power - Multi VT, multi drive strengths - Leakage, area recovery using ECOs - Power gating (header/footer) - Body bias - overdrive technique - Control LVT usage in PD (allow only % of LVT cells) - 3-sigma versus 2-sigma corners - Reduces yield but better leakage - Characterized library at power corner (Scaling factors across corners will be pessimistic)