3. Why ICs
Integration improves
Size (Submicron)
Speed
Power
Complexity
Smaller size of IC components yields higher speed and lower power consumption.
Integration reduce manufacturing costs
(almost) no manual assembly
4. Discrete vs Integrated Circuit Design
Active devices, capacitors, and
resistor
All possibleComponents
Schematic Capture,
Simulation, extraction, LVS,
layout and routing
Schematic Capture,
Simulation, PC Board Layout
CAD
Must be considered before
design
Generally complete testing is
possible
Testing
Model parameters vary widelyModel parameters well knownSimulation
Must be included in the designNot ImportantParasitics
Layout, Verification and
Extraction
PC layoutPhysical Implementation
Very dependentIndependentFabrication
No (kit parts)YesBreadboarding
Poor absolute accuraciesWell knownComponent Accuracy
IntegratedDiscreteActivity / Item
5. History
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
Mechanical computing devices
Used decimal number system
Could perform basic arithmetic
operations
Even store and execute
Problem: Too complex and expensive!
6. ENIACENIAC -- The first electronic computer (1946)The first electronic computer (1946)
17,468 vacuum tubes
7,200 crystal diodes
1,500 relays
70,000 resistors
10,000 capacitors
30 tons
63 m²
150 kW
5,000 simple addition
or subtraction operations
Problem: Reliability issues and excessive power consumption!
7. Invention of the Transistor
Vacuum tubes invented in 1904 by Fleming
Large, expensive, power-hungry, unreliable
Invention of the bipolar transistor (BJT) 1947
Shockley, Bardeen, Brattain – Bell Labs
8. First Integrated Circuit
integrated circuit 1958 Jack Kilby – Texas Instruments
A device having multiple electrical components and their interconnects manufactured
on a single substrate.
9. Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor
1971
2300 transistors
108 KHz operation
PMOS only (10 um process)
10. IntelIntel Pentium 4Pentium 4 MicroMicro--ProcessorProcessor
2000
42 million transistors
2 GHz operation
0.18 um
12. VLSI technological growth based on:
• Feature size
• Gate count of a chip
• Transistor count of a chip
• Operating frequency of a chip
• Power consumption of a chip
• Power density in a chip
• Size of a device used in chip
13. Moore’s Law
Gordon Moore
Intel Co-Founder
In 1965, Gordon Moore noted that
the number of transistors on a chip
doubled every 18 to 24 months.
16. EXACTLY HOW SMALL (AND POWERFUL) IS 45 NANOMETERS
45nm Size Comparison
o A nail = 20 million nm
o A human hair = 90,000nm
o Ragweed pollen = 20,000nm
o Bacteria = 2,000nm
o Intel 45nm transistor = 45nm
o Rhinovirus = 20nm
o Silicon atom = 0.24nm
1.000.000.000nm = 1m
17. Expected CMOS Downsizing from History to Future
100nmIn early 1990
500nmIn early 1980
1micro-meterIn late 1970
Expected
Downsizing
LimitEra
5nm gate lenght p-channel MOSFET has been reported in the research level
Today
Intel plans to introduce processors built on 32nm technology in 2009
(H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-
10- nm Planar-Bulk-CMOS Devices using Lateral Junction Control”, IEDM Tech., Dig., pp.989-991, Washington DC, December, 2003)
Future
The ultimate limit of downsizing is the distance of atoms in silicon crystals.
(about 0.3nm )
History
22. Worldwide IC Foundry Centers
6Europe & Israel
25
Other Asian Countries
(China, Taiwan, Singapore, Korea)
12Japan
16USA
The total number of IC
Foundry CenterCountry
23. ITRS - International Technology Roadmap for Semiconductors
60005500450040002500MAXIMUM NUMBER OF I/O PINS
180W175W170W160W130WMAXIMUM POWER DISSIPATION
0.6V0.6V0.9V1.2V1.5VMINIMUM SUPPLY VOLTAGE
3.5GHz3GHz2.5GHz2GHz1.6GHzMAXIMUM CLOCK FREQUENCY
200GBits70GBits25GBits10GBits2GBitsDRAM CAPACITY
16 Billion6 Billion3 Billion1 Billion400MNUMBER OF TRANSISTOR (LOGIC)
900mm2
800mm2
750mm2
600mm2
400mm2
CHIP SIZE
35nm50nm70nm100nm130nmTECHNOLOGY
20142011200820052002YEAR
Predictions of the worldwide semiconductor / IC
industry about its own future prospects..
24. ASIC Design Strategies
Design is a continuous tradeoff to achieve
performance specs with adequate results in all
the other parameters.
Performance Specs - function, timing, speed,
power
Size of Die - manufacturing cost
Time to Design - engineering cost and schedule
Ease of Test Generation & Testability -
engineering cost, manufacturing cost, schedule
26. From Sand to IC
2-inch to 12-inch wafers
When Intel first began making chips,
the company printed circuits on 2-inch wafers.
Now the company uses both 300-millimeter (12-inch)
and 200-millimeter (8-inch) wafers, resulting in larger
chip yields and decreased costs.
The larger wafers can yield more than
twice as many chips, achieving an economy
of scale that Intel says will save 30% in
manufacturing costs for each wafer.
27. Scaling & Integration Analogy
12 inch wafer:
300 mm diameter
23 billion components
Earth:
13000 km diameter
7 billion people
28. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)
29. IC Classification
Circuit technology(BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)
34. Why CMOS
Power dissipation only during switching
(circuitry dissipates less power when static)
Higher packing density – lower manufacturing cost per device
MOS devices could be scaled down more easily
Bipolar transistors can operate at higher frequencies than CMOS
(usefull for microwave applications )
35. Bipolar vs. MOS Transistor
FasterSlowerTechnology Improvement
GoodPoorSwitch Implementation
Smaller for short
channelSlightly largerSmall Signal Output Resistance
PoorGoodNoise (1/f)
50 GHz (0.25µm)100 GHzCutoff Frequency(fT)
43Number of Terminals
0.4mS (W=10L)4mSgm at 100MicroAmper
FastFasterSpeed
Low but can be largeModerate to HighPower Dissipation
CMOSBJTCATEGORY
36. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style(Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)
38. Full Custom Design
Custom design involves the entire design of the IC, down to the smallest detail of
the layout.
No restriction on the placement of functional blocks and their interconnections
Highly optimized, but labor intensive..
Designer must be an expert in VLSI design
Design time can be very long (multiple months)
Involves the creation of a a completely new chip
Fabrication costs are high
41. Standart Cell Design
Designer uses a library of standard cells; an automatic place and route
tool does the layout.
Each standard cell contains a single gate of AND, OR, NOT etc.
Standard cells can be placed in rows and connected with wires
Routing done on “channels” between the rows.
All cells are the same height but vary in width.
All cells have inputs and outputs on top or bottom
of cell.
Design time can be much faster than full custom because layout is
automatically generated.
44. Gate Array Design
Pre-fabricated array of gates (could be NAND).
(Gates already created on a wafer; only need to add the interconnections.)
Entire chip contains identical gates
normally 3- or 4-input NAND or NOR gates.
10,000 – 1,000,000 gates can be fabricated within a single IC depending
on the technology used.
A routing tool creates the masks for the routing layers and "customizes" the
pre-created gate array for the user's design
Manufacture of interconnections requires only metal deposition
Fabrication costs are cheaper than standard cell or full custom because the
gate array wafers are mass produced
The density of gate arrays is lower than that of custom IC’s
This style is often a suitable approach for low production volumes.
46. FPGA Design
Pre-fabricated array of programmable logic and interconnections.
Programmable interconnects between the combinational logic, flip-flops
and chip Inputs and Outputs
Field Programmable devices are arrays of logic components whose
connectivity can be established simply by loading appropriate configuration
data into device’s internal memory.
No fabrication step required, avoid fabrication cost and time
Very good for prototype design because many FPGAs are
re-usable.
51. DIGITAL
Regular, hierarchical and modular
Designed at the system level
Standardized
Components must have fixed values
Simplified device models
Available synthesis EDA tools
Designed at the system level
(top-down)
Short design time
First time successful prototyping
Irregular /hardly hierarchical
Designed at the circuit level
Customized
Components must have a continuum values
Required precision modeling
Hard to find synthesis tools
Mixed bottom-up top-down
Longer design time
More spins for prototyping
Difficult to test
Less power consumption
ANALOG
Mixed Mode
52. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size(SSI, MSI, LSI, VLSI, ULSI, GSI)
54. System-on-a-Chip (SoC)
Integrating all or most of the components of a hybrid system on a single substrate
(silicon or MCM), rather than building a conventional printed circuit board.
More compact system
realization
Higher speed
Better reliability
Less expensive
56. Advatages of 3D-ICs
Improved packing density
Noise immunity
Improved total power due to reduced wire length/lower capacitance
Superior performance
The ability to implement added functionality
http://www.research.ibm.com/journal/rd/504/topol.html
59. Future of CMOS Technology
Future Lithography Techniques (electron-beam lithography, X-ray
lithography, Excimer laser)
Novel transistor structures (SOI, double-gate MOSFETs , High-k (dielectric
constant) gate insulatoror technology)
Wiring and interconnections (aluminium-based inter-connects are being
replaced by lower-resistance copper ; low-k (dielectric constant) interlayer for
interconnects)
Control of Power and heat generation (New cooling technologies,
Changeable clock frequency and supply voltage )
