ARM DATAFLOW, REGISTER SET

1. EMBEDDED & REAL TIME SYSTEMS
mr.C.KARTHIKEYAN
AP/ECE/RMKCET

2. UNIT II ARM
PROCESSOR
AND
PERIPHERALS

3. SYLLABUS
 ARM Architecture Versions
ARM Architecture
Instruction Set
Stacks and Subroutines
Features of the LPC 214X Family
 Peripherals
The Timer Unit
Pulse Width Modulation Unit
UART
Block Diagram of ARM9 and ARM Cortex M3 MCU
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4. FUNDAMENTALS
COMPUTER TAXANOMY ARCHITECTURE (Arrangement of MEMORY)
DIFFERENCE BETWEEN COMPUTER & MOBILE PHONE SoC
REAL TIME APPLICATIONS
INTRODUCTION TO ARM PROCESSOR
DATAFLOW
ARM ARCHITECTURE
OPERATION
MODES
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5. COMPUTER TAXANOMY ARCHITECTURE
1.VON NEUMANN ARCHITECTURE
Hardware requirements- LESS
Space requirements- LESS SPACE
Controlling-Simple
since either data or instructions
are to be fetched at a time.
Speed of execution- slow
since it cannot fetches the data and instructions
at the same time
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6. 2.HARVARD ARCHITECTURE (HP)
Hardware requirements- more
Space requirements-more SPACE
Speed of execution- fast
because the processor fetches
data and instructions simultaneously .
Controlling-complex
since data and instructions are
to be fetched simultaneously
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7. 3.CISC
Flexibility
Performance
Command length varies
More no. of clock cycles even for small code
Emphasis on hardware
More RAM, Less Register
RTA: PC/ LAPTOPS FOR PROCESSING HEAVY GRAPHIC GAMING &
COMPUTING COMPLEX EQUATIONS
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8. 4.RISC
Rigidity
Performance
Command length equal
Less no. of clock cycles even for long code
Emphasis on software
Less RAM, More Register
RTA: MOBILE PHONES, ANDROIS, IOS, TABLETS FOR HIGHER
RESPONSE
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9. APLLICATIONS
SMARTPHONES-Snapdragon Processors or Media Tek Processors
LAPTOP/ DESKTOP-Intel and AMD Processor
⬡ The Snapdragon central processing unit (CPU) uses the ARM RISC
instruction set, and a single SoC may include multiple CPU cores.
⬡ It comes with graphics processing unit (GPU), which provides high-quality
graphics and superior gaming experiences.
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10. 10
ARM BASED PRODUCTS

11. “ Introduction to ARM
Processor” - One of the
most licensed and thus
widespread processor cores
in the world
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12. Advanced RISC
Machine

13. NOMENCLATURE
⬡ ARMxyzTDMIEJFS
⬡ – x: series
⬡ – y: MMU
⬡ – z: cache
⬡ – T: Thumb
⬡ – D: debugger
⬡ – M: Multiplier (MAC)
⬡ – I: Embedded ICE (built-in debugger hardware)
⬡ – E: Enhanced instruction
⬡ – J: Jazelle (JVM)
⬡ – F: Floating-point
⬡ – S: Synthesizible version (source code version for EDA Tools)
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14. 14
1.ARM (32)
2.THUMB (16)
3.JAZELLE
3 STATES OF OPERATION
3 DIFFERNET INSTRUCTION SETS

15. ARM
FEATURES
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16. 32 bit MC
32 bit ALU
32 bit Data bus
32 bit data stored in 4
consecutive locations
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⬡ All instructions are in aligned form
⬡ ARM7- Von Neumann
⬡ ARM9- Harvard

17. Load/store model
8086(CISC)
ADD CL,BL
ADD CL,[2000]
⬡ ARM (RISC)
⬡ REGISTER BASED
⬡ LOAD THE DATA INTO THE REGISTR
⬡ PERFORM OPERATION
⬡ EXECUTE RESULT STORE IN REGISTER
⬡ RIGID, HP
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18. 18
3 Stage PIPELINE

19. ARM DATA FLOW
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20. REGISTERS
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ARM has 37 registers
All registers are of 32 bits
R0-r15 DATA REGISTER (R0-R12 GPR)
r13, r14, and r15 perform special functions
r13: stack pointer – push & pop operation
r14: link register – one fn. to another, to know the return back address
r15: program counter- which instruction to be executed
Two status registers
CPSR: Current Program Status Register (1)
SPSR: Saved Program Status Register (5)

21. 7 MODES OF OPERATION
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22. REGISTER SET
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23. BINARY EQUIVALENT VALUES FOR DIFFERENT MODES
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24. PSR -Program Status Register
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BITS (0-7 ) C –CONTROL, BITS (8-15) X- EXTENSION , BITS (16-23) S - STATUS, BITS (24-31) F-FLAGS

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Thanks!
Any questions?