The document discusses microcontroller architecture and output compare interrupts. Output compare interrupts are triggered by timers and can be used to enforce real-time processing. The microcontroller contains registers that store timer values and output compare values, and generates an interrupt when the timer equals the compare value. Programmers can enable interrupts and use output compares to generate timing events and trigger interrupt service routines.

1. Structure of Microcontroller EA, RST, ALE, PSEN ROM COUNTER INPUTS OSC INTERRUPT CONTROL 4 I/O PORTS BUS CONTROL SERIAL PORT EXTERNAL INTERRUPTS CPU ON - CHIP RAM ETC TIMER 0 TIMER 1 ADDRESS/DATA TXD RXD P0 P1 P2 P3

2. Structure of Microcontroller

11. IEN0 - Interrupt enable register 0

12. CMOD - PCA counter mode register (address D9H) bit allocation

13. CMOD - PCA counter mode register (address D9H) bit allocation

14. CCON - PCA counter control register (address 0D8H) bit description

15. CCON - PCA counter control register (address 0D8H) bit description

16. CCAPMn - PCA modules compare/capture register

17. CCAPMn - PCA modules compare/capture register

18. PCA IN COMPARE MODE