2. History Overview .
CPU Architecture.
Memories.
Microcontroller Families.
3. CPU design divide into three parts:
The datapath
does all of the actual data processing
A control unit
uses the programmer’s instructions to tell
the datapath what to do
An instruction
set is the programmer’s interface to CPU
5. • Processor data-path is the hardware part of the
processor that performs the processing
operations.
• It helps understand how data is transferred
from one component of the processor to
another component
6. Three main functionality of a processor
datapath :
o Computations ALU
o Fast temporary storage Register file
o Large memory storage RAM
7. 1)Arithmetic Logic Unit :
» A and B are two n-bit inputs
» FS is m-bit function select
code
» F is n-bit result
» Status bits to provide more
information about result F :
► Z = 1 result is zero
► N = 1 result is negative
► V = 1 signed overflow
► C = 1 carry out
A
B
Output
Flags
Control & Selection
8. 2)Register File :
» A number of registers
grouped together
» You can read two
registers at once by
supplying AA and BA
» You can write at a register
using the DA and D inputs
and setting WR = 1
9. • CPU Registers are classified into two main
categories
– User-visible registers
– Control and status registers
2)Register File :
10. • User-visible registers
– These are registers that are visible to the programmer
to use for programming the processor.
– They are further categorized as follows:
• General purpose:
– Used by programmer to store data, or perform
operations on them
• Data
– Can be used for storage/retrieval of data only,
not for operations
2)Register File :
11. • User-visible registers
• Address Registers:
– They are dedicated for storing addresses specific to
memory operations frequently required
– Examples are: Stack pointer & Segment pointer
• Condition Codes:
– They are flags that are set by the CPU as a result of
logic and arithmetic operations
2)Register File :
12. • Control and Status Registers
– These are a set of essential registers for proper operation. They are
usually not visible to the programmer, although some of them are
so
– Examples are:
• Program Counter (PC):
Contains the address of the instruction to be fetched
• Instruction Register (IR):
Contains the instruction most recently fetched
• Memory address register (MAR): Contains the address
of the location in the memory to be fetched/stored
• Memory buffer register (MBR):
Contains the data to be loaded/stored in the memory
2)Register File :
16. The control unit connects programs with the datapath :
» It converts program instructions into control signals
for the datapath : WR, DA, AA, BA, MB, FS, MW, MD
» It executes program instructions in the correct
sequence
» It generates the “constant” input for the datapath
The datapath also sends information back to the control
unit For instance, the ALU status bits V, C, N, Z can be
inspected by branch instructions to alter a program’s
control flow
18. • Execution of instructions is the basic responsibility of the control unit
• The action of executing an instruction is called “instructioncycle”
• Instruction cycles are broken down into smaller actions micro-
operations
• micro-operations ,the action is simple and accomplishes very little
• Thecontrolunit‟sheartbeatistheprocessorclock,each“clock
cycle”,thecontrolunitperformsoneormoremicro-operations
19. • The instruction cycle is broken down into:
– Fetch Cycle
– Indirect Cycle
– Execute Cycle
– Interrupt Cycle
20. CPU operation Code (binary) Code (hex)
Add register R1 to register R0 0000.1100.0000.0001 0C01
instruction cycle
21. Four main modules in the control unit :
» Program Counter (PC) register
Keep track of the instruction currently being executed
» Instruction decoder
takes a machine language instruction and produces the matching control
signals for the datapath
» Instruction RAM
Memory that contains the instructions of the program
» Branch control unit
Determines the next value of the PC depending on the jumps / branches
instructions
22. Program Counter (PC) :
»Addresses the instruction memory
»On each clock cycle, the counter
does one of two things.
►If Load = 0, the PC increments, so
the next instruction will be executed.
►If Load = 1, the PC is updated with Data,
which represents some address specified
in a jump or branch instruction
Load
Data
ADRS
Instruction
RAM
OUT
PC
23. Instruction Decoder :
» The instruction decoder takes a
machine language instruction and
produces the matching control signals
for datapath
» These signals tell the datapath which
registers or memory locations to
access and what ALU operations to
perform
(to the datapath)
Load
Data
DA AA BA MB FS MDWR MW
PC
ADRS
Instruction
RAM
OUT
Instruction Decoder
24. Branch Control Unit :
» decides what the PC’s next
value should be :
► For jumps, the PC should be loaded
with the target address specified in
the instruction
► For branch instructions, the PC
should be loaded with the target
address only if the corresponding
status bit is true
► For all other instructions, the PC
should just increment
DA AABA MB FS MD WR MW
V
C
N
Z
Branch
Control
ADRS
Instruction
RAM
OUT
Instruction Decoder
PC
25. ► The basic control unit
On each clock cycle:
» An instruction is read from the
instruction memory
» The instruction decoder generates
the matching datapath control
word
» Datapath registers are read and
sent to the ALU or the data
memory
» ALU or RAM outputs are written
back to the register file
» The PC is incremented, or reloaded
for branches and jumps.
DA AABA MB FS MD WR
V
C
N
Z
Branch
Control
ADRS
Instruction
RAM
OUT
Instruction Decoder
PC
26. Harvard arch.:
includes two memory units :
► An instruction memory holds the
program
► A separate data memory is used
for computations
► The advantage is that we can read
an instruction and load or store
data in the same clock cycle
Harvard Vs Von Neumann
27. Harvard Vs Von Neumann
Von Neumann arch.:
includes one memory unit :
a single main memory that holds both
program instructions and data
28. W R
DA
AA
B A
FS
V
C
N
Z
MB
MD
MW
constant
DA AA B A MB FS MD W R M W
V
C
N
Z
Branch
Control
PC
ADRS
Instruction
RAM
OUT
Instruction Decoder
D
Register file
A B
1 0
Mux B
ADRS DATA
Data RAM
OUT
A B
ALU
G
0 1
Mux D
Control Unit Datapath
That is it the whole processor
29. RISC CISC
Reduced Instruction Set Computer Complex Instruction Set Computer
optimize execution of instructions by
single instruction limiting capabilities
integrate several functionalities in one
instruction
The compiler or programmer
synthesizes complicated operations
by combining several simple
instructions. (ex: divide operation)
The Compiler is simple as has wide
verity of instructions to perform the
complicate operation
30. RISC CISC
simple operations that can each
execute in a single cycle
the instructions are often take many cycles to
execute.
have a large general-purpose register
set.
dedicated registers for specific purposes
Any register can handle with ALU dedicated registers specific for ALU operation
ALU can’t deal with Memory directly ALU can deal with memory directly
Due to Memory accesses are costly :
the core can operate at higher clock
frequencies.
and operate at lower clock frequencies
Separate load and store instructions
transfer data between the register bank
and external memory are needed to all
ALU operations
Separate load and store instructions transfer
data between the register bank and external
memory aren’t needed to all ALU
operations
Helps to pipeline execution of instructions
31. History Overview .
CPU Architecture.
Memories.
Microcontroller Families.
32.
33. ROM Types
MROM
• Masked ROM
• Programmed by the manufacturer.
• The term„masked‟comesfromthemanufacturingprocess
• In case of a large-scale production, the price is very low.
PROM
• Programmable rom
• Also called One time programmable ROM
• enables programmer to download a program into it one time only.
• If an error is detected after downloading, the only thing you can do is to download
the correct program to another chip.
34. UV EPROM
• UV Erasable Programmable ROM
• It enables data to be erased under strong ultraviolet light.
• After a few minutes it is possible to download a new program.
EEPROM
• ELECTRICALLY ERASABLE PROGRAMMABLE ROM
• can be erased by exposing it to an electrical charge
Flash Memory
• Invented in the 80s in the laboratories of INTEL
• Represented as the successor to the UV EPROM.
• Can be written and cleared practically an unlimited number of times,
• most microcontrollers are manufactured in flash technology.
ROM Types
35. SRAM:
• Static random access memory
• uses multiple transistors, typically four to six, for each memory cell
• doesn't have a capacitor in each cell.
DRAM:
• Dynamic random access memory
• has memory cells with a paired transistor and capacitor requiring constant
refreshing.
ROM Types
36. History Overview .
CPU Architecture.
Memories.
Microcontroller Families.
