2. REPORT
ON
ARM7
Submitted to.
Department of ECE
IMRAN SIR
Submitted by.
Name: Abu Md Abdullah Choudhury
Roll no: 12K31A0402
Branch: ECE

3. ARM Microcontroller

4. Features of LPC2148:
PACKAGE
16/32-bit ARM7TDMI-S microcontroller in a tinyLQFP64 package.
MEMORY:
40 kB of on-chip static RAM
512 kB of on-chip flash program memory.
SPEED
128 bit wide interface/accelerator enableshigh speed 60 MHz operation.
In-System /In-Application Programming (ISP/IAP)
via on-chip boot-loader software.
Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms .
USB 2.0 Full Speed compliant
Device Controller with 2 kB of endpoint RAM.
In addition, the LPC2146/8 provide 8kB of on-chip RAM accessible to USB by DMA.
ADC:
Two 10-bit A/D
Converters(AD0 andAD1)
Provide a total of 14 analog inputs
conversion times as low as 2.44 us per channel.
DAC:
Single 10-bit
D/A (digital to analog)
converter provides variable analog output.
TIMERS:
Two 32-bit timers/external event counters
Each timer with four capture and four compare
Channels PWM unit (six outputs)
Watchdog timer

5. RTC:
Low power real-time clock with independent power and dedicated 32
kHz clock input.
Serial Interfaces:
I2C-bus:
Two Fast I2C-bus with 400 Kbit/s
Serial communication:
Two UARTs (UART0.UART1)
SPI (Serial Peripheral Interface)
And SSP(Synchronous Serial Port) with buffering and variable data length
capabilities
Fast GPIO:
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
INTERRUPTS:
Vectored interrupt controller with 16 configurable priorities and vector addresses.
9 edge or level sensitive external interrupt pins available.
60 MHz maximum
CPU clock available from programmable on-chip
PLL with settling Time of 100s.
OSCILLATOR:
On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30 MHz and with an external oscillator up to 60MHz.
Power saving modes:
Idle mode
Power-down mode
Operating Voltage
CPU operating voltage range of 3.0 V to 3.6 V(3.3 V ± 10 %) with 5 V tolerant I/O
pads.

6. Applications of LPC2148 :
1. Industrial control
2. Medical systems
3. Access control
4. Communication gateway
5. Embedded soft modem
6. General purpose applications
ARM7TDMI-S architecture:
ARM( advanced RISC machine)
T : supports Thumb (16-bit) instruction set
D : contains Debug extensions
M : enhanced (relative to earlier ARM cores) 32x8 Multiplier
I : Embedded ICE microcell

7. S : synthesizable (ie. distributed as RTL rather than a hardened layout)
The CoreMP7 subsystem peripherals include:
AHB- Lite interface
APB interface
AHB to APB bridge
Memory controller
Interrupt controller
Timers
Serial interface
ARM7TDMI-S architecture:

8. Software tools for ARM7 (LPC2148):
Programming languages for Microcontrollers:
 Assembly language
 Embedded ‘C’,C++
 JAVA
 UNIX
 LINUX (RTOS)
 WIN CE (RTOS)

9. An assembly language is a low-level programming language for
a computer, microcontroller, or other programmable device, in which each
statement corresponds to a single machine code instruction. Each assembly
language is specific to a particular computer architecture, in contrast to
most high-level programming languages, which are generally portable across
multiple systems.
Assembly language is converted into executable machine code by a utility
program referred to as an assembler; the conversion process is referred to
as assembly, or assembling the code.
Embedded C is a set of language extensions for the C Programming
language by the C Standards committee to address commonality issues that
exist between C extensions for different embedded systems. Historically,
embedded C programming requires nonstandard extensions to the C language
in order to support exotic features such as fixed-point arithmetic, multiple
distinct memory banks, and basic I/O operations.

10. DIFFERENCE BETWEEN NON EMBEDDED ‘C’ AND EMBEDDED ‘C’:
Though C and embedded C appear different and are used in different contexts,
they have more similarities than the differences. Most of the constructs are
same; the difference lies in their applications.
C is used for desktop computers, while embedded C is for microcontroller
based applications. Accordingly, C has the luxury to use resources of a desktop
PC like memory, OS, etc. While programming on desktop systems, we need not
bother about memory. However, embedded C has to use with the limited
resources (RAM, ROM, I/Os) on an embedded processor. Thus, program code
must fit into the available program memory. If code exceeds the limit, the
system is likely to crash.

11. Compilers for C (ANSI C) typically generate OS dependant
executables. Embedded C requires compilers to create files to be downloaded to
the microcontrollers/microprocessors where it needs to run. Embedded
compilers give access to all resources which is not provided in compilers for
desktop computer applications.
Embedded systems often have the real-time constraints, which is usually not
there with desktop computer applications.
Embedded systems often do not have a console, which is available in case of
desktop applications.
So, what basically is different while programming with embedded C is the
mindset; for embedded applications, we need to optimally use the resources,
make the program code efficient, and satisfy real time constraints, if any. All
this is done using the basic constructs, syntaxes, and function libraries of ‘C’.
Software tools
 Assembler
 Compiler
 Cross compiler
 Debugger
 Simulator
 IDE
 ICE
 JTAG
A compiler is a computer program (or set of programs) that transforms source
code written in a programming language (the source language) into another
computer language (the target language, often having a binary form known
as object code). The most common reason for wanting to transform source code
is to create an executable program.

12. ASSEMBLER

13. DEBUGGER
Different IDE’s for microcontrollers
PIC Microcontroller from Microchip
Microchip'sIDE - MPLAB IDE
Microchip'sC18 –C Compiler2.
8051 Microcontroller
Kiel assembler
Proview
ASM513.
Atmel and Atmega Microcontroller
AVR Studio
C Programming in AVR Studio using WinAVR C Compiler
Arm Microcontroller
keil4 assembler

14. JTAG for microcontrollers
JTAG for microcontrollers
Software tools for ARM7 (LPC2148

15. Keil IDE for ARM7
LCD interfacing with LPC2148(ARM7):

16. 16X2 LCD Basics :
This particular chinese LCD i.e JHD162A has KS0066U controller or similar to
the famous HD44780U.
It Consists of 2 Rows with 16 Characters on each.
It has a 16 pin Interface. Operates on 5V and has LED backlight.
Works in 2 Modes :
1) Instruction Mode : Used for initializing and configuring LCD before we can
use it & during operation.
2) Data Mode : Displays the respective characters for codes supplied to it via
Data Pins.
3) data transfer modes
 4 bit mode
 8 bit mode

17. 1) Power Pins : Pin 1,2,3,15,16
2) Control Pins : Pin 4,5,6
3) Data Pins : Pin 7 to 14
Contrast Voltage (VEE) : Instead of using a trim pot just connect a 1K resistor
to VEE in series and ground it. That gives the best contrast of what I’ve seen.
RS(4 pin) – short for Register select (Control Pin) : Used to switch been
Instruction and Data Mode. RS = High for Instruction Mode and RS = Low for
Data mode.
R/W(5 pin) – Read or Write (Control Pin): R/W = High for Read Mode and
R/W = Low for Write. Since we are going to use Write Mode only we will
permanently ground it using a pull-down resistor of 4.7K Ohms. Caution : If
you are planning to use Read Mode with 3.3V MCUs you’ll need a Bi-directional
level shifter which can shift 5V to 3.3V and Vice-Versa.
Enable( 6 Control Pin) : This is similar to a trigger pin. Each Data/Instruction
is executed by the LCD module only when a pulse is applied to Enable pin.
More specifically the it is executed at the falling edge of the pulse.
UART Communication for LPC2148:
Computers transfer data in two ways:
Parallel
Often 8 or more lines (wire conductors) are used to transfer data to a device
that is only a
few feet away
Serial
To transfer to a device located many meters away, the serial method is used
The data is sent one bit at a time

18. Serial data communication uses two methods
Synchronous method transfers a block of data at a time
Asynchronous method transfers a single byte at a time

19. A protocol is a set of rules agreed by both the sender and receiver on
How the data is packed
How many bits constitute a character
When the data begins and ends
Asynchronous serial data communication is widely used for character-oriented
transmissions

21. UART (Universal Asynchronous Receiver Transmitter) are one of the basic
interfaces which provide a cost effective simple and reliable communication
between one controller to another controller or between a controller and PC.
Interfacing UART
Fig. 1 shows how to interface the UART to microcontroller. To communicate
over UART or USART, we just need three basic signals which are namely, RXD
(receive), TXD (transmit), GND (common ground). So to interface UART with
LPC2148, we just need the basic signals.
Hardware connections:
RS-232 Level Converter
Usually all the digital ICs work on TTL or CMOS voltage levels which cannot be
used to communicate over RS-232 protocol. So a voltage or level converter is

22. needed which can convert TTL to RS232 and RS232 to TTL voltage levels. The
most commonly used RS-232 level converter is MAX232.
This IC includes charge pump which can generate RS232 voltage levels (-10V
and +10V) from 5V power supply. It also includes two receiver and two
transmitters and is capable of full-duplex UART/USART communication.
RS-232 communication enables point-to-point data transfer. It is commonly
used in data acquisition applications, for the transfer of data between the
microcontroller and a PC.
The voltage levels of a microcontroller and PC are not directly compatible with
those of RS-232, a level transition buffer such as MAX232 be used.
Different registers in UART
PINSEL0 (0,1,2) pin select register
U0LCR line control register
U0DLL divisor latch LSB
U0LSR line statues register
U0THR transmitter holding register
U0RBR receiver buffer register
Pin Function Select Registers (PINSEL)
To enable you to select which pin functions you would like to use, you need to
use one of the the three PINSEL registers: PINSEL0, PINSEL1 and PINSEL2.
Which register you use depends on which pin you want to modify.
PINSEL0 contains GPIO pins 0.0 to 0.15
PINSEL1 contains GPIO pins 0.16 to 0.31
PINSEL2 is a special case, and is used to control whether pins 1.16..31 are
used as GPIO pins, or as a Debug port in combination with a hardware JTAG
debugger. Since we are using a hardware JTAG debugger in all of these
tutorials, these pins will not be available to use as GPIO during testing and
development (they are used by the JTAG device itself).

23. Each associated 'pin' in PINSEL0 and PINSEL1 is assigned a 2-bit address.
P0.0, for example, uses the first two bits in PINSEL0, P0.1 uses the next two
bits, and so on, until you end up with the following layout:
Function Selection Bits:
Binary
Value
Selected Function
00
Primary (default) function (always
GPIO)
01 First alternate function
10 Second alternate function
11 Third alternate function
PINSEL0
bits Symbol Value function
1-0 P0.0 00 GPIO
01 TXD0 (UART0)
10 PWM1
11 reserved
3-2 P0.1 00 GPIO
01 RXD0 (UART0)
10 PWM3
11 EINT0

24. 17-16 P0.8 00 GPIO
01 TXD1(UART 1)
10 PWM4
11 Reserved
19-18 P0.9 00 GPIO
01 RXD1(UART 1)
10 PWM6
11 EINT3
THR : Transmitter holding register (WO)
The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB
represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access
the
U0THR. The U0THR is always Write Only.
RBR : Receiver buffer register (RO)
The RBR, receiver buffer register contains the byte received if no FIFO is used,
or the oldest unread byte with FIFO's. If FIFO buffering is used, each new read
action of the register will return the next byte, until no more bytes are present.
Bit 0 in the LSR line status register can be used to check if all received bytes
have been read. This bit wil change to zero if no more bytes are present.

25. ADC (analogy to digital conversion):
Features of ADC on LPC2148:-
• 10 bit successive approximation analog to digital converter (one in LPC2141/2
and two in LPC2144/6/8).
• Input multiplexing among 6 or 8 pins (ADC0 and ADC1).
• Power-down mode.
• Measurement range 0 V to VREF (typically 3 V; not to exceed VDDA voltage
level).
• 10 bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple inputs.

26. • Optional conversion on transition on input pin or Timer Match signal.
• Global Start command for both converters (LPC2144/6/8 only).
Hardware pin description for ADC 0 and ADC 1 :
ADC 0:
P0.28/AD0.1/CAP0.2/MAT0.2
P0.29/AD0.2/CAP0.3/MAT0.3
P0.30/AD0.3/EINT3/CAP0.0
P0.25/AD0.4/AOUT
P0.4/SCK0/CAP0.1/AD0.6
P0.5/MISO0/MAT0.1/AD0.7
ADC 1:
P0.6/MOSI0/CAP0.2/AD1.0
P0.10/RTS1/CAP1.0/AD1.2
P0.12/DSR1/MAT1.0/AD1.3
P0.13/DTR1/MAT1.1/AD1.4
P0.15/RI1/EINT2/AD1.5
P0.21/PWM5/AD1.6/CAP1.3
P0.22/AD1.7/CAP0.0/MAT0.0
Registers for ADC 0 and ADC 1
 AD0CR (A/D Control Register)
 PCONP (Power Control for Peripherals)
 PINSEL1 (Pin function select register 1)
 AD0GDR(A/D Global Data Register)
 AD0DR(A/D Data Registers ADDR0 to ADDR7)

27. AD0CR (A/D Control Register):
7:0 SEL
Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted.
For
AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7.
15:8 CLKDIV
The VPB clock (PCLK) is divided by (this value plus one) to produce the clock for
the
A/D converter, which should be less than or equal to 4.5 MHz.
16 BURST
BURST = 1
The AD converter does repeated conversions at the rate selected by the CLKS
field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant1 in the SEL field,
then
higher numbered 1-bits (pins) if applicable. Repeated conversions can be
terminated by
clearing this bit,but the conversion that’s in progress when this bit is cleared will
be
Completed.
BURST =0
AD0CR (A/D Control Register):
19:17 CLKS
This field selects the number of clocksused for each conversion in Burst mode,
and the
number of bits of accuracy of the result in the RESULT bits of ADDR, between 11
clocks
(10 bits) and 4 clocks (3 bits).
000 11 clocks /10 bits

28. 001 10 clocks / 9bits
010 9 clocks /8 bits
011 8 clocks /7 bits
100 7 clocks /6 bits
101 6 clocks /5 bits
110 5 clocks /4 bits
111 4 clocks /3 bits
AD0CR (A/D Control Register)
20 – Reserved.
21 PDN
1 The A/D converter is operational.
0 The A/D converter is in power-down mode.
23:22 - Reserved.
26:24 START
When the BURST bit is 0, these bits control whether and when an A/D
conversion is
started:
000 No start (this value should be used when clearing PDN to 0).
001 Start conversion now.
010 Start conversion when the edge selected by bit 27 occurs on
011 Start conversion when the edge selected by bit 27 occurs on
100 Start conversion when the edge selected by bit 27 occurs on MAT0.1.
101 Start conversion when the edge selected by bit 27 occurs on MAT0.3.
110 Start conversion when the edge selected by bit 27 occurs on MAT1.0.
111 Start conversion when the edge selected by bit 27 occurs on MAT1.1.
27 EDGE

29. 1 This bit is significant only when the START field contains 010-111. In these
cases: Startconversion on a falling edge on the selected CAP/MAT signal.
0 Start conversion on a rising edge on the selected CAP/MAT signal.
31:28 - Reserved
Power Control for Peripherals register (PCONP ):
Reserved, user software should not write ones to reserved bits. The value read
from are served bit is not defined.
1 PCTIM0 Timer/Counter 0 power/clock control bit. 1
2 PCTIM1 Timer/Counter 1 power/clock control bit. 1
3 PCUART0 UART0 power/clock control bit. 1
4 PCUART1 UART1 power/clock control bit. 1
5 PCPWM0 PWM0 power/clock control bit. 1
6 Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
7 PCI2C0 The I2C0 interface power/clock control bit. 1
8 PCSPI0 The SPI0 interface power/clock control bit. 1
9 PCRTC The RTC power/clock control bit. 1
10 PCSPI1 The SSP interface power/clock control bit. 1
11 – Reserved.
12 PCAD0 A/D converter 0 (ADC0) power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
18:13 - Reserved, I2C1 The I2C1 interface power/clock control bit. 1
20 PCAD1 A/D converter 1 (ADC1) power/clock control bit.
Note: Clear the PDN bit in the AD1CR before clearing this bit, and set
this bit before setting PDN.
30:21 - Reserved, user software should not write ones to reserved bits.
Thevalue read from a reserved bit is not defined.
31 PUSB USB power/clock control bit.

30. ADDR ( A/D data register) :
AD0DR0 channel 0
AD0DR1 channel 1
AD0DR2 channel 2
AD0DR3 channel 3
AD0DR4 channel 4
AD0DR6 channel 6
AD0DR7 channel 7
Programming for read ADC0 channel 0 :
I2C (Inter- Integrated circuit)Protocal :
I2C interfaces I2C0 and I2C1
Features
 Standard I2C compliant bus interfacesthat may be configured asMaster,
Slave, or Master/Slave.
 Arbitration between simultaneously transmitting masters without
corruption of serialdata on the bus.
 Programmable clockto allow adjustment of I2C transfer rates.
 Bidirectional data transfer between masters and slaves.

31.  Serial clock synchronization allows devices with differentbit rates to
communicate via one serial bus.
 Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer.
 The I2C-bus may be used for test and diagnostic purposes.
I2C operating modes:
 Master Transmitter mode
 Master Receiver mode
 Slave Receiver mode
 Slave Transmitter mode
Master Transmitter mode
Master Receive mode

32. Slave Receiver mode
Slave Transmitter mode
Important registers in I2C Communication
I2CONSET (I2C Control Set register)
I2DAT ( I2C data register )
I2ADR (I2C Slave Address register)
I2SCLH (I2C SCL High duty cycle register)
I2SCLL ( I2C SCL Low duty cycle register)
I2CONCLR (I2C Control Clear register)

33. I2CONSET (I2C Control Set register)
I2DAT (I2C Control Set register)
I2ADR (I2C Slave Address register)
I2SCLH (I2C SCL High duty cycle register)
I2SCLL ( I2C SCL Low duty cycle register)
I2CONCLR (I2C Control Clear register)

34. INITIALIZATION:
• I2ADR is loaded with the part’s own slave address and the general call bit (GC)
• The I2C interrupt enable and interrupt priority bits are set
• The slave mode is enabled by simultaneously setting the I2EN and AA bits in
I2CON and the serial clock frequency (for master modes) is defined by loading
CR0 and CR1 in I2CON. The master routines must be started in the main
program.
1. Load I2ADR with own Slave Address, enable general call recognition if
needed.
2. Enable I2C interrupt.
3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave
functions. For
Master only functions, write 0x40 to I2CONSET.
Start Master Transmit function
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Write
bit.

35. 3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being
sent.
6. Exit
Start Master Receive function
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the
Read bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be
received.
6. Exit
REAL TIME CLOCK (RTC)

36. Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra Low Power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month,
Year, Day of Week, and Day of Year.
• Dedicated 32 kHz oscillator or programmable presale from VPB clock.
• Dedicated power supply pin can be connected to a battery or to the main 3.3
RTC external 32 kHz oscillator component selection

37. Important registers in RTC
Important registers in RTC

38. Interrupt Location Register (ILR )
Clock Tick Counter Register (CTCR)
Consolidated Time register 0 (CTIME0):

39. Consolidated Time register 1 (CTIME1 )
Time counter group

40. TIMERS
Timer/Counter TIMER0 and TIMER1
Features
• A 32-bit Timer/Counter with a programmable 32-bit Presale.
• Counter or Timer operation
• Up to four 32-bit capture channels per timer, that can take a snapshot of the
timer
value when an input signal transitions. A capture event may also optionally
generate
an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the
following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
Timer/Counter TIMER0 and TIMER1

41. APPLICATIONS
• Interval Timer for counting internal events.
• Pulse Width Demodulator via Capture inputs.
• Free running timer.
Here is the list of all CAPTURE signals, together with pins on where
they can be selected:
 CAP0.0 (3 pins): P0.2, P0.22 and P0.30
 CAP0.1 (2 pins): P0.4 and P0.27
 CAP0.2 (3 pin): P0.6, P0.16 and P0.28
 CAP0.3 (1 pin): P0.29
 CAP1.0 (1 pin): P0.10
 CAP1.1 (1 pin): P0.11
 CAP1.2 (2 pins): P0.17 and P0.19
 CAP1.3 (2 pins): P0.18 and P0.21
Here is the list of all MATCH signals, together with pins on where they can be
selected:
 MAT0.0 (2 pins): P0.3 and P0.22
 MAT0.1 (2 pins): P0.5 and P0.27
 MAT0.2 (2 pin): P0.16 and P0.28

42.  MAT0.3 (1 pin): P0.29
 MAT1.0 (1 pin): P0.12
 MAT1.1 (1 pin): P0.13
 MAT1.2 (2 pins): P0.17 and P0.19
 MAT1.3 (2 pins): P0.18 and P0.20
Important registers
 VPBDIV (VLSI Peripheral Bus divider )
 PINSEL0 (pin select register)
 T0PR ( TIMER0 presale register)
 T0TCR (TIMER0 control register)
 T0CCR (TIMER0 capture control register )

43. VPBDIV (VLSI Peripheral Bus divider )
T0PR ( TIMER0 presale register)
The 32-bit Prescale Register specifiesthe maximum value for the Prescale
Counter
T0TCR (TIMER0 control register)

44. T0CCR (TIMER0 capture control register )
INTERRUPTS:
Features of interrupts in LPC2148
• ARM PrimeCell™ Vectored Interrupt Controller
• 32 interrupt request inputs
• 16 vectored IRQ interrupts
• 16 priority levels dynamically assigned to interrupt requests
• Software interrupt generation

45. The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs these
are into 3 types
FIQ ( Fast interrupt request )
vectored IRQ
non-vectored IRQ
FIQ ( Fast interrupt request )
Fast Interrupt request (FIQ) requests have the highest priority. If more than
one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ
signal to the ARM processor
vectored IRQ
Vectored IRQs have the middle priority, but only 16 of the 32 requests can be
assigned to
this category. Any of the 32 requests can be assigned to any of the 16 vectored
IRQ slots,

46. among which slot 0 has the highest priority and slot 15 has the lowest.
non-vectored IRQ
Non-vectored IRQs have the lowest priority.
Interrupt sources
VIC control register

47. External interrupts
 External interrupt 0 (EINT0)
 External interrupt 1 (EINT 1)
 External interrupt 2 (EINT2)
 External interrupt 3 (EINT3)
External interrupts hardware pins
 External interrupt 0 (EINT0) P0.1 , P0.16
 External interrupt 1 (EINT 1) P0.3 , P0.14
 External interrupt 2 (EINT2) P0.7 ,P0.15
 External interrupt 3 (EINT3) P0.20 . P0.30
Hardware circuit diagram

48. Example program for external interrupts

49. TRIAC (BT 136 interfacing with 8051)
GSM modem interfacing

50. GSM/GPRS module is used to establish communication between a computer
and a GSM-GPRS system. Global System for Mobile communication (GSM) is
an architecture used for mobile communication in most of the
countries. Global Packet Radio Service (GPRS) is an extension of GSM that
enables higher data transmission rate. GSM/GPRS module consists of a
GSM/GPRS modem assembled together with power supply circuit and
communication interfaces (like RS-232, USB, etc) for computer. The MODEM is
the soul of such modules.
GSM/GPRS MODEM
GSM/GPRS MODEM is a class of wireless MODEM devices that are designed
for communication of a computer with the GSM and GPRS network. It requires
a SIM (Subscriber Identity Module) card just like mobile phones to activate
communication with the network. Also they have IMEI (International Mobile
Equipment Identity) number similar to mobile phones for their identification. A
GSM/GPRS MODEM can perform the following operations:
1. Receive, send or delete SMS messages in a SIM.
2. Read, add, search phonebook entries of the SIM.
3. Make, Receive, or reject a voice call
The MODEM needs AT commands, for interacting with processor or controller,
which are communicated through serial communication. These commands are
sent by the controller/processor. The MODEM sends back a result after it
receives a command. Different AT commands supported by the MODEM can be
sent by the processor/controller/computer to interact with the GSM and GPRS
cellular network.
AT commands' syntax

51. Command Line
Mobile Station (Cell phones and SIM)
AT commands with a GSM/GPRS MODEM or mobile phone can be used to
access following information and services:
1. Information and configuration pertaining to mobile device or MODEM
and SIM card.
2. SMS services.
3. MMS services.
4. Fax services.
5. Data and Voice link over mobile network.
Command, Information response and Result Codes:
Basic AT commands for GSM interfacing

52. AT+CMGS command sends an SMS message to a GSM phone.
AT+CMGF=1
OK
AT+CMGS="+31628870634"
>This is the text message.
+CMGS: 198 OK
AT+CMGF=1
OK
AT+CMGL="ALL"
+CMGL: 1,"REC
UNREAD","+31628870634",,"11/01/09,10:26:26+04"
This is text message 1
+CMGL: 2,"REC UNREAD","+31628870634",,"11/01/09,10:26:49+04“
This is text message 2
OK
AT+CMGD=1
OK
AT+CMGD=2
OK
GPS receiver interface with 8051
Global Positioning System (GPS) GPS technology became a reality through
the efforts of the American military, which established a satellite-based
navigation system consisting of a network of 24 satellites orbiting the earth.
GPS is also known as the NAVSTAR (Navigation System for Timing and
Ranging).