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DOMINO LOGIC CIRCUIT (VLSI)
- 1. EE141 © Digital Integrated Circuits2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić November 2002.
- 2. EE141 © Digital Integrated Circuits2nd Combinational Circuits 2 Issues in Dynamic Design 1: Charge Leakage CL Clk Clk Out A Mp Me Leakage sources CLK VOut Precharge Evaluate Dominant component is subthreshold current
- 3. EE141 © Digital Integrated Circuits2nd Combinational Circuits 3 Solution to Charge Leakage CL Clk Clk Me Mp A B Out Mkp Same approach as level restorer for pass-transistor logic Keeper
- 4. EE141 © Digital Integrated Circuits2nd Combinational Circuits 4 Issues in Dynamic Design 2: Charge Sharing CL Clk Clk CA CB B=0 A Out Mp Me Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
- 5. EE141 © Digital Integrated Circuits2nd Combinational Circuits 5 Charge Sharing CL Clk Clk CA B=0 A VOut VX Slide by Kia
- 6. EE141 © Digital Integrated Circuits2nd Combinational Circuits 6 Charge Sharing CL Clk Clk CA B=0 A VOut VX Slide by Kia
- 7. EE141 © Digital Integrated Circuits2nd Combinational Circuits 7 Charge Sharing Mp Me VDD Out A B = 0 CL Ca Cb Ma Mb X CLVDD CLVout t Ca VDD VTn VX – + = or Vout Vout t VDD – Ca CL ------- - VDD VTn VX – – = = Vout VDD Ca Ca CL + --- ------------------ - – = case 1) if Vout < VTn case 2) if Vout > VTn B = 0 Clk X CL Ca Cb A Out Mp Ma VDD Mb Clk Me
- 8. EE141 © Digital Integrated Circuits2nd Combinational Circuits 8 Solution to Charge Redistribution Clk Clk Me Mp A B Out Mkp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
- 9. EE141 © Digital Integrated Circuits2nd Combinational Circuits 9 Issues in Dynamic Design 3: Backgate Coupling CL1 Clk Clk B=0 A=0 Out1 Mp Me Out2 CL2 In Dynamic NAND Static NAND =1 =0
- 10. EE141 © Digital Integrated Circuits2nd Combinational Circuits 10 Backgate Coupling Effect -1 0 1 2 3 0 2 4 6 Time, ns Clk In Out1 Out2
- 11. EE141 © Digital Integrated Circuits2nd Combinational Circuits 11 Issues in Dynamic Design 4: Clock Feedthrough CL Clk Clk B A Out Mp Me Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
- 12. EE141 © Digital Integrated Circuits2nd Combinational Circuits 12 Clock Feedthrough -0.5 0.5 1.5 2.5 0 0.5 1 Clk Clk In1 In2 In3 In4 Out In & Clk Out Time, ns Clock feedthrough Clock feedthrough
- 13. EE141 © Digital Integrated Circuits2nd Combinational Circuits 13 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)
- 14. EE141 © Digital Integrated Circuits2nd Combinational Circuits 14 Cascading Dynamic Gates Clk Clk Out1 In Mp Me Mp Me Clk Clk Out2 V t Clk In Out1 Out2 V VTn Only 0 1 transitions allowed at inputs!
- 15. EE141 © Digital Integrated Circuits2nd Combinational Circuits 15 Domino Logic In1 In2 PDN In3 Me Mp Clk Clk Out1 In4 PDN In5 Me Mp Clk Clk Out2 Mkp 1 1 1 0 0 0 0 1
- 16. EE141 © Digital Integrated Circuits2nd Combinational Circuits 16 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort Better noise margin
- 17. EE141 © Digital Integrated Circuits2nd Combinational Circuits 17 Why Call it Domino? Clk Clk Ini PDN Inj Ini Inj PDN Ini PDN Inj Ini PDN Inj Like falling dominos!
- 18. EE141 © Digital Integrated Circuits2nd Combinational Circuits 18 Footer needed? Clk Clk Out1 In Clk Clk Out2 Slide by Kia (fig by Rabaey)
- 19. EE141 © Digital Integrated Circuits2nd Combinational Circuits 19 Designing with Domino Logic Mp Me VDD PDN Clk In1 In2 In3 Out1 Clk Mp Me VDD PDN Clk In4 Clk Out2 Mr VDD Inputs = 0 during precharge Can be eliminated!
- 20. EE141 © Digital Integrated Circuits2nd Combinational Circuits 20 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage VDD Clk Mp Out1 In1 1 0 VDD Clk Mp Out2 In2 VDD Clk Mp Outn Inn In3 1 0 0 1 0 1 0 1 1 0 1 0
- 21. EE141 © Digital Integrated Circuits2nd Combinational Circuits 21 Domino Layout Slide by Kia
- 22. EE141 © Digital Integrated Circuits2nd Combinational Circuits 22 np-CMOS In1 In2 PDN In3 Me Mp Clk Clk Out1 In4 PUN In5 Me Mp Clk Clk Out2 (to PDN) 1 1 1 0 0 0 0 1 Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN
- 23. EE141 © Digital Integrated Circuits2nd Combinational Circuits 23 NORA Logic In1 In2 PDN In3 Me Mp Clk Clk Out1 In4 PUN In5 Me Mp Clk Clk Out2 (to PDN) 1 1 1 0 0 0 0 1 to other PDN’s to other PUN’s WARNING: Very sensitive to noise!
- 24. EE141 © Digital Integrated Circuits2nd Combinational Circuits 24 Differential (Dual Rail) Domino A B Me Mp Clk Clk Out = AB !A !B Mkp Clk Out = AB Mkp Mp Solves the problem of non-inverting logic 1 0 1 0 on off
- 25. EE141 © Digital Integrated Circuits2nd Combinational Circuits 25 Multiple-Output Domino
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