Personal Information
Entreprise/Lieu de travail
Egypt Egypt
Profession
Senior Digital Verification Engineer
Secteur d’activité
Electronics / Computer Hardware
À propos
Sameh El-Ashry is working as senior digital verification engineer, with 6+ years of industry experience. He has worked as senior digital verification engineer at Si-Vision, and his work involves the verification of digital wireless communication IPs including PHYs, basebands, MACs, and verification of SerDes IPs. He participated as an expert reviewer at Design Automation Conference (DAC). He has worked as hardware verification engineer in MED at Mentor, a Siemens Business, Cairo, Egypt, where he participated in two of the major projects of the team. He has different published papers at international conferences for memory controllers, NoC, coverage, assertions, and UVM. He received the M.Sc.
Mots-clés
uvm
systemverilog
verification
noc
verilog
digital design
egypt
vsli
vhdl
chip design
ral
coverage
regression
testcase
scripting
planning
simulation
emulation
riscv
dft
power aware
Tout plus
Présentations
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•
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•
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•
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•
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•
il y a 14 ans
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•
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Verification Engineer - Opportunities and Career Path
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•
il y a 7 ans
Personal Information
Entreprise/Lieu de travail
Egypt Egypt
Profession
Senior Digital Verification Engineer
Secteur d’activité
Electronics / Computer Hardware
À propos
Sameh El-Ashry is working as senior digital verification engineer, with 6+ years of industry experience. He has worked as senior digital verification engineer at Si-Vision, and his work involves the verification of digital wireless communication IPs including PHYs, basebands, MACs, and verification of SerDes IPs. He participated as an expert reviewer at Design Automation Conference (DAC). He has worked as hardware verification engineer in MED at Mentor, a Siemens Business, Cairo, Egypt, where he participated in two of the major projects of the team. He has different published papers at international conferences for memory controllers, NoC, coverage, assertions, and UVM. He received the M.Sc.
Mots-clés
uvm
systemverilog
verification
noc
verilog
digital design
egypt
vsli
vhdl
chip design
ral
coverage
regression
testcase
scripting
planning
simulation
emulation
riscv
dft
power aware
Tout plus