Sameh El-Ashry

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Sameh El-Ashry is working as senior digital verification engineer, with 6+ years of industry experience. He has worked as senior digital verification engineer at Si-Vision, and his work involves the verification of digital wireless communication IPs including PHYs, basebands, MACs, and verification of SerDes IPs. He participated as an expert reviewer at Design Automation Conference (DAC). He has worked as hardware verification engineer in MED at Mentor, a Siemens Business, Cairo, Egypt, where he participated in two of the major projects of the team. He has different published papers at international conferences for memory controllers, NoC, coverage, assertions, and UVM. He received the M.Sc.

uvm systemverilog verification noc verilog digital design egypt vsli vhdl chip design ral coverage regression testcase scripting planning simulation emulation riscv dft power aware

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Sameh El-Ashry

How to create SystemVerilog verification environment?

Chipions session 2021 - VLSI career

Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage

On Error Injection for NoC Platforms: A UVM-based Practical Case Study

A reusable verification environment for NoC platforms using UVM

verification_planning_systemverilog_uvm_2020

On the verification of configurable nocs in simulation and hardware emulation a uvm based tool

Functional verification techniques EW16 session

Code Management Workshop