This document presents a new architecture for a hybrid partitioned SRAM-based ternary content-addressable memory (TCAM) that introduces a parity bit to improve search speed and reduce power consumption. The proposed design adds a parity bit segment to the original TCAM data to first check parity bit matching before comparing the full search word. Simulation and synthesis results show the new design achieves lower delay and power compared to existing hybrid partitioned SRAM-based TCAM architectures.