Pass Transistor Logic(PTL)
• Only N_MOS Transistors are Used to design the logic.
• Input Signals are Applied to both Gate and
When A=1 Upper NMOS is ON, So
o/p is F=B
When A=0 Upper
NMOS is ON, So o/p is F=B
CMOS Transmission Gate
Actually, It is a Parallel Connection of
N_MOSFET and P-MOSFET that realizes a
Inputs to the gates of N-MOSFET and P-
MOSFET are Complementary to each other.
Working of CMOS Transmission Gate
When C=1 and C^=0
Nodes A&B-----------Short Circuited
Input Logic is Transferred to Output
When C=10and C^=1
Nodes A&B-----------Open Circuited
Actually ,this is Called High-Impedance State.
It is used as a supplement for the CMOS logic circuits.
In the pseudo-NMOS logic, the PUN is realized by a
single PMOS transistor.
The gate terminal of the PMOS transistor is connected
to the ground.
P-MOS Transistor remains permanently in the ON state
Depending on the input combinations, output goes low
through the PDN.
Only the NMOS logic (Qn) is driven by the input
Qp acts as an active load for Qn.
Except for the load device(P-MOS), the Pseudo-NMOS
gate circuit is identical to the pull-down
network(PDN) of the CMOS gate.
Advantages & Disadvantages of Pseudo N-MOS Logic
1) Uses less number of transistors as compared to
2) Geometrical area and delay gets reduced as it
requires less transistors.
3) Low power dissipation.
1.The main drawback of using a Pseudo NMOS gate
instead of a CMOS gate is that the always on PMOS
load conducts a steady current when the output
voltage is lower than VDD.
2.Layout problems are critical.
It is one of the alternate method of reducing
It is similar to Pseudo –NMOS Logic except one
additional NMOS Transistor(MN) Connected between
PDN and Ground.
PMOS Transistor in PUN and additional NMOS
Transistor(MN) in PDN are Operated by a Clock Signal
Dynamic Logic Circuit Operates in 2 Phases of Single
Clock Pulse ϕ
Phase-1 (Pre-Charge Phase ϕ =0)
Here, Output is Pre Charged to Logic High Level.
Phase-2 (Evaluation Phase ϕ=1)
Here, Output is evaluated based on applied Input Logic.
It is a Slightly modified Version of Dynamic CMOS
A Static Inverter is Connected at the Output of
each dynamic CMOS logic blocks.
Addition of Inverter Solves the Problem of
Cascading of dynamic CMOS logic Circuits.
It is Suitable for only Non-Inverting Logic(the
expression having no complement over whole
For Inverting the logic the expression must be
reorganized before it can be realized using
Domino CMOS Logic.
Case -1 when ϕ = 0
Output is Pre charged to logic high and O/P of static
Inverter is Low.
Case -2 When ϕ =1
O/P is either 0 (or) 1 Output of static Inverter
can make 0 1 in Evaluation. So, Irrespective of I/P
and O/p of Static Inverter can’t make 1 0 in
For, N- Input Logic function we require,
2N Transistors-- Static CMOS
N+2 Transistors- Dynamic CMOS
N+2+2 Transistors Domino CMOS
A pull-up p-block and a complementary n-block pull-
down structure represent p and n-transistors
However, the logic in this case is connected to the
output only during the ON period of the clock.
When ø = 1 the circuit acts an inverter , because
transistors Q3 and Q4 are ‘ON’ .
It is said to be in the “Evaluation mode”. Therefore
the output Z changes its Previous value.
When ø = 0 the circuit is in hold mode, because
transistors Q3 and Q4 ‘OFF’ .
It is said to be in the “Pre Charge mode”. Therefore
the output Z remains its previous value.