RISC-V Summit presentation by Morten Borup Petersen. Ripes is available at https://github.com/mortbopet/Ripes

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December 8-10 | Virtual Event

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December 8-10 | Virtual Event
Ripes
Teaching Computer Architecture Through
Visual and Interactive Simulators
#RISCVSUMMIT Morten Borup Petersen

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About me
● 2015 - 2019 : B.Sc. EE @ DTU - Technical University of Denmark
● Spring 2019 : Intern embedded software engineer @ ARM Cambridge
● 2019 - now : M.Sc. CS @ EPFL - École polytechnique fédérale de Lausanne
Agenda
● Educational simulators and motivation for Ripes
● Demo 1: Ripes overview, usage & processor models
● Ripes - What’s inside? VSRTL
● Demo 2: C Integration & cache simulation

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Undergraduate course coverage:
1. ISAs & assembly level programming
2. Microarchitecture
● Single-cycle, pipelined
● Hazards, forwarding
● Memory system
Teaching computer architecture
Why not have a single application
to experiment with all of the core
concepts while unifying simulator
capabilities?
Simulator capabilities*:
● Online (Venus, Vulcan, ...) ⇨ Zero setup
● Functional (Spike, QEMU, ...) ⇨ Efficiently execute binaries
● Visual (WebRISC-V, ...) ⇨ Investigate datapath during execution

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In books...

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What makes a good educational simulator?
1. Little/no setup
2. Eliminate sources of frustration
3. Make it visual
4. Make it capable
The simulator should make you want to explore RISC-V!
Simulator requirements
First point of contact - make it enjoyable!

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Ripes
“A visual processor simulator and assembly editor for the RISC-V ISA”
ISA & Implementations
● Simulates various in-order architectures
● Implements the RV32(I/M) instruction set
Editor & Interaction
● Integrated assembly editor
● Interactive memory viewer
● Animated datapath
High(er) level concepts
● Cache simulation
● C toolchain integration

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Ripes has been used at ...
And others...

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Ripes - Timeline
2017
2018
2019
2020
Initial commit
(ISA simulator)
5-stage pipeline
visualization, built-in
assembler & editor
VSRTL initial commit
(circuit visualization
framework)
Simulator & visualization
overhaul (VSRTL) ⇨ multiple
processor models
Cache simulation, C
toolchain integration
2021

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Ripes - Editor
Simulator controls
Stage contents
Source code Disassembled
executable

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Ripes - Processor Animated datapath
Register view
Instruction view

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Ripes - Processor

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Ripes - Memory
Scrollable memory
view
Cache geometry
configuration
Cache policy
configuration
Cache access
statistics
Cache animation

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Demo 1: Ripes overview, usage & processor models

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Ripes v1.0: Some lessons learned
1. Circuit description: Need a correct and versatile simulation framework
● Allows for design modification
● Multiple processor designs
2. Graphics: Circuit visualization should be generated from circuit description
● Allows for interaction with circuit (highlighting wires, show/hide components etc.)
3. Simulation: Need ability to step back and forward in time
● Allows for investigating interesting pipeline situations
What’s Inside?
Conclusion:
1. Needed a framework to provide all of the above
2. Notably, these requirements may be fully decoupled from the notion
of “simulating a processor”

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Visual Simulation of Register Transfer Logic
A framework for describing cycle-accurate simulators which provides an automatically generated visualization of
the simulated circuit
What’s Inside? - VSRTL

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VSRTL
Graphics
VSRTL
Components
VSRTL
Core
What’s inside? - VSRTL
VSRTL Architecture
Circuit description
● (Simple) HDL embedded in C++
● Simulator, circuit primitives (ports, entities, wires, …)
● VSRTL Standard library: logic gates, registers, multiplexers, …
● Component widgets
● Reflect simulator state changes
● Visualization “place and route”
Ripes processor models

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VSRTL
Graphics
VSRTL
Components
VSRTL
Core
What’s inside? - VSRTL
VSRTL Architecture
…
*: VSRTL Core was/is an interesting exercise but we should be able
to visualize circuits generated through commonly used HDLs
Future:
● Add FIRRTL parser/simulator backend
⇨ Chisel will have a simulator with visualization
VSRTL Graphics decoupled from VSRTL Core
● Why? No one needs another HDL*
● VSRTL Graphics expects some simulator
backend adhering to its interface

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● Ships with 4 processor models
- Single cycle
- 5 stage
- 5 stage w/o hazard detection
- 5 stage w/o forwarding or hazard
detection
● Different views for each processor model
● Interactive
● Reversible simulation
Ripes v2
VSRTL Integration

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● Ships with 4 processor models
● Different views for each processor model
- Standard
- Extended
+ control, forwarding, hazard units
+ port widths
● Interactive
● Reversible simulation
Ripes v2
VSRTL Integration

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● Ships with 4 processor models
● Different views for each processor model
● Interactive
- Port values (w/ radix selection)
- Wire highlighting
● Reversible simulation
Ripes v2
VSRTL Integration

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Demo 2: C Integration & cache simulation

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Going further...
Low-hanging fruit Beyond the basics VSRTL
Branch prediction
I/O Out-of-order
Processors
ALU
ALU FPU LSU
IM
Sched
RF
?

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December 8-10 | Virtual Event
Ripes on GitHub:
github.com/mortbopet/Ripes
morten_bp@live.dk
linkedin.com/in/mortbopet/

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December 8-10 | Virtual Event
Thank you for joining us.
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