Vlsi titles 2014_2015_ME & M.Tech

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VLSI Titles for
ME & M.Tech,

S3 INFOTECH +919884848198
VEDIC AND REVERSIBLE ARCHITECTURES:
PROJECT
CODE
NAME OF THE PROJECTS YEAR
EPVVR-001
EPVVR-002
EPVVR-003
EPVVR-004
EPVVR-005
EPVVR-006
EPVVR-007
EPVVR-008
EPVVR-009
EPVVR-010
EPVVR-011
EPVVR-012
EPVVR-013
Low power Square and Cube Architectures Using Vedic Sutras
High Speed Vedic Multiplier Designs
Binary Division Power Models for High-Level Power Estimation of FPGA-
Based DSP Circuits
Design of Dedicated Reversible Quantum Circuitry for Square Computation
ASIC Design of Reversible Multiplier Circuit
All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing
Ancilla and Garbage Bits
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
Eliminating Synchronization Latency Using Sequenced Latching
Area-Delay Efficient Binary Adders in QCA
Design and Performance Analysis of Reversible Logic based ALU using
Hybrid Single Electron Transistor
Synthesis of ESOP-based Reversible Logic using Negative Polarity Reed-
Muller Form
An Optimized Design of Reversible Quantum Comparator
IEEE 2014
IEEE 2014
IEEE 2014
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IEEE 2014
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IEEE 2014

S3 INFOTECH +919884848198
EPVVR-014
EPVVR-015
EPVVR-016
EPVVR-017
EPVVR-018
EPVVR-019
EPVVR-020
EPVVR-021
EPVVR-022
EPVVR-023
EPVVR-024
EPVVR-025
EPVVR-026
EPVVR-027
EPVVR-028
EPVVR-029
EPVVR-030
EPVVR-031
EPVVR-032
Approach to design a compact reversible low power binary comparator
Realization of 2:4 reversible decoder and its applications
Novel High Speed Vedic Mathematics Multiplier using Compressors
Performance Evaluation of FFT Processor Using Conventional and Vedic
Algorithm
Design a DSP Operations using Vedic Mathematics
Design of High Speed Low Power Multiplier using Reversible logic: a Vedic
Mathematical Approach
Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
Design of Low Logical Cost Adders using Novel Parity Conserving Toffoli
Gate
Design of Testable Reversible Sequential Circuits
Reversible Logic Synthesis of k-Input, m-Output Lookup Tables
Analysis and Improvement of Transformation-based Reversible Logic
Synthesis
Reversible Logic Implementation of AES Algorithm
Energy Efficient Code Converters using Reversible Logic Gates
Efficient Approaches to Design a Reversible Floating Point Divider
Parity Preserving Logic based Fault Tolerant Reversible ALU
Design of Low Power Comparator Circuit Based on Reversible Logic
Technology
An Optimal Design of a Fault Tolerant Reversible Multiplier
Behavioral Model of Integrated Qubit Gates for Quantum Reversible Logic
Design
A Novel Optimization Method for Reversible Logic Circuit Minimization
IEEE 2014
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S3 INFOTECH +919884848198
EPVVR-033
EPVVR-034
EPVVR-035
EPVVR-036
EPVVR-037
EPVVR-038
EPVVR-039
EPVVR-040
EPVVR-041
EPVVR-042
EPVVR-043
Optimized Power Performance and Simulation of Reversible Logic
Multiplexer
Design and Implementation of Fast FPGA Based Architecture for Reversible
Watermarking
Cycle based Reversible Logic Synthesis Approach
Contemplation of Synchronous Gray Code Counter and its Variants using
Reversible Logic Gates
An Evolutionary Approach to Reversible Logic Synthesis using Output
Permutation
Design and Implementation of Logical Cost Efficient Nanometric Fault
Tolerant Reversible BCD Adder
Optical logic circuits using double controlled logic gate
High Performance Vedic BCD Multiplier and Modified Binary to BCD
Converter
Vedic Divider - A High Performance Computing algorithm for VLSI
Applications
Reciprocal unit based on Vedic mathematics for signal processing applications
Design And FPGA Implementation Of Binary Squarer Using Vedic
Mathematics
IEEE 2013
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S3 INFOTECH +919884848198
REAL TIME SIMULATION:
PROJECT
CODE
EPVRT-001
EPVRT-002
EPVRT-003
EPVRT-004
EPVRT-005
EPVRT-006
EPVRT-007
Simulation of energy efficient Bi-directional Visitor Counting Machine on
FPGA
Using FPGA to Control a Virtual Sorting System
FPGA Implementation of Advanced Health Care system using Zig-Bee enabled
RFID Technology
FPGA-Based Design of Grid Friendly Appliance Controller
Embedded System for Home Automation Using SMS
Design of an Academic Microcontroller and its Application to Authenticated
Encryption
Mapping Complex Algorithm into FPGA with High Level Synthesis
Reconfigurable chips with High Level Synthesis compared with CPU, GPGPU
IEEE 2014
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S3 INFOTECH +919884848198
SIGNAL PROCESSING APPLICATION:
PROJECT
CODE
EPVSP-001
EPVSP-002
EPVSP-003
EPVSP-004
EPVSP-005
EPVSP-006
EPVSP-007
EPVSP-008
EPVSP-009
FPGA based Partial Reconfigurable FIR Filter Design
FPGA Based Implementation of High Speed Tunable Notch Filter Using
Pipelining and Unfolding
Design and Implementation of High Throughput and Area Efficient Hard
Decision Viterbi Decoder in 65nm Technology
High Speed Multiplier for FIR Filter Design using Window
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications
for Efficient FIR Filter Implementation
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks
With Low Adder-Count
Scalable low power FFT/IFFT architecture with dynamic bit width
configurability
A Power Efficient Video Encoder using Reconfigurable Approximate
IEEE 2014
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IEEE 2014
IEEE 2014
IEEE 2014
IEEE 2014

S3 INFOTECH +919884848198
EPVSP-010
EPVSP-011
EPVSP-012
EPVSP-013
EPVSP-014
EPVSP-015
EPVSP-016
EPVSP-017
EPVSP-018
EPVSP-019
EPVSP-020
EPVSP-021
EPVSP-022
EPVSP-023
EPVSP-024
EPVSP-025
Arithmetic Units
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite
Impulse Response Filters
Scaled Radix-2/8 Algorithm for Efficient Computation of Length-N=2m DFTs
FPGA Based Implementation & Power Analysis of Parameterized Walsh
Sequences
Improved 8-Point Approximate DCT for Image and Video Compression
Requiring Only 14 Additions
An Efficient Hardware Based MAC Design in Digital Filters with Complex
Numbers
Razor Based Programmable Truncated Multiply and Accumulate, Energy-
Reduction for Efficient Digital Signal Processing
Design and Implementation of an MSI number based Image Watermarking
Architecture in Transform Domain
High throughput pipelined 2D Discrete cosine transform for video compression
Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR
Digital Filter
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
Power Evaluation of Sobel Filter on Xilinx Platform
Improved matrix multiplier design for high-speed digital signal processing
applications
Embedded Complex Floating Point Hardware Accelerator
An Efﬁcient VLSI Architecture of a Reconﬁgurable Pulse-Shaping FIR
Interpolation Filter for Multistandard DUC
Area Efficient High Speed Low Power Multiplier Architecture For Multirate
Filter Design
The Implementation of FIR Low-pass Filter Based on FPGA and DA
IEEE 2014
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S3 INFOTECH +919884848198
EPVSP-026
EPVSP-027
EPVSP-028
EPVSP-029
EPVSP-030
EPVSP-031
EPVSP-032
EPVSP-033
EPVSP-034
EPVSP-035
EPVSP-036
EPVSP-037
EPVSP-038
EPVSP-039
Design and Implementation of a 1024-point High-speed FFT Processor Based
on the FPGA
Processor Arrays Generation for Matrix Algorithms Used in Embedded
Platforms
MIN-MAX: A Counter-Based Algorithm for Regular Expression Matching
Multiplier-less VLSI Architecture of 1-D Hilbert Transform pair using
Biorthogonal Wavelets
Design of Optimized CIC Decimator and Interpolator in FPGA
FPGA based Architectures for High Performance Adaptive FIR Filter Systems
An Efficient Implementation of Synthesis Filter Bank and Digital Spectrum
Processing on Xilinx Virtex-5 FPGA for Onboard Transparent Processor
Design and FPGA Implementation of an 2D Gaussian Surround Function with
Reduced On-Chip Memory Utilization
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple
Constant Multiplication/Accumulation
Low Power Multiply Accumulate Unit (MAC) for Future Wireless Sensor
Networks
VLSI Architecture of Multiplierless DWT Image Processor
High performance and low-power finite impulse response filter based on ring
topology with modified retiming serial multiplier on FPGA
An FPGA Based Low Power Multiplier for FFT in OFDM Systems Using
Precomputations
New Approximate Multiplier for Low Power Digital Signal Processing
IEEE 2013
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S3 INFOTECH +919884848198
ARCHITECTURE:
PROJECT
CODE
EPVAR-001
EPVAR-002
EPVAR-003
EPVAR-004
EPVAR-005
EPVAR-006
EPVAR-007
EPVAR-008
EPVAR-009
EPVAR-010
EPVAR-011
EPVAR-012
Design of a Low-Error Fixed-Width Radix-8 Booth Multiplier
Gate Mapping Automation for Asynchronous NULL Convention Logic
Circuits
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
Power- and Area-Efficient Approximate Wallace Tree Multiplier for Error-
Resilient Systems
A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s
Recoding Algorithm
4-2 Compressor Design with New XOR-XNOR Module
Design and Estimation of delay, power and area for Parallel prefix adders
Fast Radix-10 Multiplication Using Redundant BCD Codes
CryptIP: An Approach for Encrypting Intellectual Property Cores with
Simulation Capabilities
A New Design of Low Power High speed CMOS Full Adder
Improved design of high-frequency sequential decimal multipliers
A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal
Converter
IEEE 2014
IEEE 2014
IEEE 2014
IEEE 2014
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IEEE 2014
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IEEE 2014
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S3 INFOTECH +919884848198
EPVAR-013
EPVAR-014
EPVAR-015
EPVAR-016
EPVAR-017
EPVAR-018
EPVAR-019
EPVAR-020
EPVAR-021
EPVAR-022
EPVAR-023
EPVAR-024
EPVAR-025
EPVAR-026
EPVAR-027
EPVAR-028
EPVAR-029
Shift Register Design Using Two Bit Flip-Flop
Implementation Of Floating Point Mac Using Residue Number System
Design and Implementation of a BIST Embedded Inter Integrated Circuit Bus
Protocol over FPGA
Data Encoding Techniques for Reducing Energy Consumption in Network-on-
Chip
Color Pass: An Intelligent User Interface to Resist Shoulder Surfing Attack
On-Chip Codeword Generation to Cope With Crosstalk
Multifunction Residue Architectures for Cryptography
Low-Latency, Low- Area Overhead and High Throughput NoC Architecture
for FPGA Based Computing System
Dual-Basis Super-serial Multipliers for Secure Applications and Lightweight
Cryptographic Architectures
Mapping Loop Structures onto Parametrized Hardware Pipelines
Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic
Digital Circuits
An Optimized Modified Booth Re-coder for Efficient Design of the Add-
Multiply Operator
32 Bit×32 Bit Multi-precision Razor-Based Dynamic Voltage Scaling
Multiplier With Operands Scheduler
Reverse Converter Design via Parallel-Prefix Adders: Novel Components,
Methodology, and Implementations
HDL Based Implementation of NxN Bit-Serial Multiplier
Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplier
Design and Implementation of Modified Signed-Digit Adder
IEEE 2014
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S3 INFOTECH +919884848198
EPVAR-030
EPVAR-031
EPVAR-032
EPVAR-033
EPVAR-034
EPVAR-035
EPVAR-036
EPVAR-037
EPVAR-038
EPVAR-039
EPVAR-040
EPVAR-041
EPVAR-042
EPVAR-043
EPVAR-044
EPVAR-045
EPVAR-046
EPVAR-047
Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail
Encoding”
Formal Verification and Debugging of Array Dividers With Auto-Correction
Mechanism
Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder
Design and Estimation of delay, power and area for Parallel prefix adders
Area–Delay–Power Efficient Carry-Select Adder
Hardware Acceleration with Pipelined Adder for Support Vector Machine
Classifier
Reviewing High-Radix Signed-Digit Adders
High-Performance 64-Bit Binary Comparator
VLSI Design of Parallel Sorter based on Modified PCM Algorithm and
Batcher’s Odd-Even Mergesort
A Space/Time Tradeoff Methodology Using Higher-Order Function
An Improved Design of Combinational Digital Circuits with Multiplexers using
Genetic Algorithm
ACMA: Accuracy-Configurable Multiplier Architecture for Error-Resilient
System-on-Chip
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-
Flops
Multioperand Redundant Adders on FPGAs
Approximate XOR/XNOR-based Adders for Inexact Computing
Multipliers using low power adder cells using 180nm Technology
The Optimum Booth Radix for Low Power Integer Multipliers
Multiple Constant Multiplication with Ternary Adders
IEEE 2014
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S3 INFOTECH +919884848198
EPVAR-048
EPVAR-049
EPVAR-050
EPVAR-051
Hardware Implementation of Truncated Multiplier Based on Multiplexer Using
FPGA
Low Power Self-Timed Carry Lookahead Adders
Comparative analysis for Hardware Circuit architecture of Wallace tree
Multiplier
Implementation Of High Speed And Low Power Hybrid Adder Based Novel
Radix 4 Booth Multiplier
IEEE 2013
IEEE 2013
IEEE 2013
IEEE 2013

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Vlsi titles 2014_2015_ME & M.Tech