Methods to reduce the Current leakage in Combinational Circuit and Sequential Circuit.

1. Leakage Current Reduction in CMOS VLSI Circuits
by Input Vector Control
Presented by : Syed Atif Naseem
EEE 533 Digital VLSI Design

2. Topics to be Covered
 Introduction
 Sources of leakage current
 Leakage minimization by input vector control
 Algorithm for MLV to linear search
 Experimental results of Combinational Circuits
 Scan Based testing for sequential circuit
 Generic Scan Chain structure
 Experimental results for sequential circuit
 Conclusion

3. Introduction
 The performance improvement has been accompanied by an
increase in power dissipation.
 Primary contributor to power dissipation i.e. charging/discharging
of load capacitance.
 Quadratically proportional to supply voltage.
 Reduction in supply voltage, decrease the threshold voltage but
significantly increase the sub-threshold leakage current
conduction.

4. Sources for leakage current:
 Source/drain junction leakage current.
 Gate direct tunneling leakage.
 Subthreshold leakage through the channel of
an OFF transistor.

5. Sub threshold leakage current
 Subthreshold leakage current is much larger
than the other leakage current components.
 Decreasing the Vth, increases the leakage
current.
 Decreasing the size of transistor, increases the
leakage current

6. Methods to reduce the leakage
current in idle mode
 By selecting minimum leakage vector
 Using multiplexer
 By modifying the gate

7. Algorithm for MLV to linear search
1) Find the trivial bounds on leakage current, LB and UB
2) C=UB, mlv=[ ]
3) Write Boolean clauses to model the circuit leakage and the
condition that total leakage >= C
4) Solve the resulting SAT problem
5) If there is no solution ,stop; C+1 is the minimum leakage and mlv
is the solution
6) mlv= the vector found by the SAT solver
7) C=C-1
8) If C > LB, stop; C+1 is the minimum leakage and mlv is the
solution
9) Go to step 3

8. A 2-to-4 decoder for single gate

9. Leakage minimization by input
vector control
 Two input Nand gate leakage
 Two nand gate with two input

10. Contribution of all gates to the total
leakage
 Total leakage=20 L00 + 15 L01 + 10 L11 + 5
L10

11. Derive the Circuit through MLV

12. Leakage Reduction By adding
Control points
Using Multiplexer
 Cut the internal line and insert the 2-to-1
multiplexer that is controlled by SLEEP signal

13. Adding the leakage current of the
multiplexer to the total leakage
 Run the linear search for MLV at modified LCN
 MLV
 Internal lines on which multiplexer are inserted

14. Modifying the gate

15. Experimental result of
Combinational Circuits
 MCNC91 bench mark

16. Energy Saving of the input vector
control mechanism

17. Energy saving for control point
addition mechanism

18. Minimum Cycles in Idle Mode

19. General model of Sequential circuit

20. Modification of circuit in test mode
of Scan chain

21. Using Scan chain for leakage
reduction

22. Leakage reduction through scan
chain

23. Local loop to save the MLV in the
active mode

24. Scan chain structure for sequential
circuit through latch

25. Applying MLV through latches in
sequential circuit

26. Experimentals results for
sequential circuit
 Apply leakage reduction method to ISCAS89

27. Conclusion
 Minimum leakage vector algorithm is developed.
 Leakage reduction through multiplexer and modifying
gates in combinational circuit.
 Scan chain through flip flop and latch used to
minimized leakage current in sequential circuit.
 Energy savings in idle mode.
 Experimental results shows the leakage reduction in
different circuits by having the minimum cycle required
in idle mode.

29. Thank You