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CS304PC:Computer Organization and Architecture session 18 floating point resentation.pptx

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CS304PC:Computer Organization and Architecture session 18 floating point resentation.pptx

  1. 1. CS304PC:Computer Organization and Architecture (R18 II(I sem)) Department of computer science and engineering (AI/ML) Session 18 by Asst.Prof.M.Gokilavani VITS 2/3/2023 Department of CSE (AI/ML) 1
  2. 2. TEXTBOOK: • 1. Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI. REFERENCES: • Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth Edition, McGraw Hill. • Computer Organization and Architecture – William Stallings Sixth Edition, Pearson/PHI. • Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition, PHI/Pearson. 2/3/2023 Department of CSE (AI/ML) 2
  3. 3. Unit III Data Representation: Data types ,Complements, fixed point Representations, Floating point representation. Computer Arithmetic: Addition and subtraction, multiplication Algorithms, Division Algorithms, Floating-point Arithmetic operations, Decimal Arithmetic unit, Decimal Arithmetic operations. 2/3/2023 Department of CSE (AI/ML) 3
  4. 4. Topics covered in session 18 2/3/2023 Department of CSE (AI/ML) 4 • Data types • Complements • Fixed point Representations • Floating point representations
  5. 5. Floating Point representation • The floating-point representation of a number has two parts • The first part represents a signed, fixed-point number – the mantissa • The second part designates the position of the binary point – the exponent. • For Example, the decimal number +6132.789 is represented in floating point with a fraction and an exponent as follows: Equivalent to +0.6132789 x 10+4 2/3/2023 Department of CSE (AI/ML) 5
  6. 6. Floating Point representation • A floating-point number is always interpreted to represent • Example: the binary number +1001.11 (with 8-bit fraction and 6-bit exponent) • Fraction: 01001110 • Exponent: 000100 • Equivalent to +(.1001110)2 x 2+4 • A floating-point number is said to be normalized if the most significant digit of the mantissa is nonzero • The decimal number 350 is normalized, 00350 is not • The 8-bit number 00011010 is not normalized • Normalize it by fraction = 11010000 and exponent = -3 • Normalized numbers provide the maximum possible precision for the floating-point number 2/3/2023 Department of CSE (AI/ML) 6
  7. 7. Other Binary Codes • Digital systems can process data in discrete form only • Continuous, or analog, information is converted into digital form by means of an analog-to-digital converter. • Gray code • Excess-3 • Excess-3 gray 2/3/2023 Department of CSE (AI/ML) 7
  8. 8. Gray code • The reflected binary or Gray code, is sometimes used for the converted digital data. • The Gray code changes by only one bit as it sequences from one number to the next. • Gray code counters are sometimes used to provide the timing sequences that control the operations in a digital system. • Binary codes for decimal digits require a minimum of four bits. • Other codes besides BCD exist to represent decimal digits. 2/3/2023 Department of CSE (AI/ML) 8
  9. 9. 2/3/2023 Department of CSE (AI/ML) 9
  10. 10. Excess-3 and Excess-3 gray 2/3/2023 Department of CSE (AI/ML) 10
  11. 11. Questions 1. 2/3/2023 Department of CSE (AI/ML) 11
  12. 12. Error Detection Codes • Transmitted binary information is subject to noise that could change bits 1 to 0 and vice versa. • An error detection code is a binary code that detects digital errors during transmission. • The detected errors cannot be corrected, but can prompt the data to be retransmitted. • The most common error detection code used is the parity bit. • A parity bit is an extra bit included with a binary message to make the total number of 1’s either odd or even . 2/3/2023 Department of CSE (AI/ML) 12
  13. 13. 2/3/2023 Department of CSE (AI/ML) 13
  14. 14. • The P(odd) bit is chosen to make the sum of 1’s in all four bits odd • The even-parity scheme has the disadvantage of having a bit combination of all 0’s . • Procedure during transmission: • At the sending end, the message is applied to a parity generator. • The message, including the parity bit, is transmitted. • At the receiving end, all the incoming bits are applied to a parity checker. • Any odd number of errors are detected. • Parity generators and checkers are constructed with XOR gates (odd function). • An odd function generates 1 iff an odd number if input variables are 1 2/3/2023 Department of CSE (AI/ML) 14
  15. 15. 2/3/2023 Department of CSE (AI/ML) 15
  16. 16. Topics to be covered in next session 19 • Addition and Subtraction algorithm 2/3/2023 Department of CSE (AI/ML) 16 Thank you!!!

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