This document asks 3 questions about a Verilog code sample that describes a 3-stage register: 1) It asks what hardware is synthesized from the original code. 2) It asks how the synthesized code would change if all = signs were replaced with <=. 3) It asks if the code can be modified by replacing = with <= such that it operates the same as the original.

1. 1. What is the hardware if the following code is synthesized?
2. What is the functional impact of changing all the equal signs in the begin/end block to <= ?
3. Is it possible to modify the code in the begin/end block by replacing = (equal sign) with <=
(less than or equal) that the synthesized code operates the same way as in case in step 1 (before
any changes). If it is, show the modification.
module reg3 (Q1, Q2, Q3, A, CLK);
input A;
input CLK;
output reg Q1, Q2, Q3;
always @ (posedge CLK)
begin
Q3 = Q2;
Q2 = Q1;
Q1 = A;
end
endmodule