This document summarizes a study analyzing the shower profile of 1-5 GeV electron beams passing through multiple layers of silicon detectors with ASIC readout. Key findings include: (1) The size of electron showers increased with increasing radiation length as expected; (2) The beam may not have been properly aligned or showers may have leaked between configurations, as seen by a discrepancy between end of 1X0 and start of 3X0; and (3) Simulation is needed to verify the shower profile results and potential beam misalignment issues.
shower study for Si-W prototype ECAL with ASIC readout
1. Shower study for 1-5 GeV energy electron
beam with ASICSKIROC readout
Elmaddin Guliyev
LLR – Ecole Polytechnique, CNRS/IN2P3
Palaiseau, France
26.09.2012- Analysis meeting
2. Tungsten plate
Detector Interface (DIF)
to DAQ (LDA)
am
be
e-
Very front-electronics (FVE8)
ASIC+Si wafer
e- beam energy: 1-5 GeV
Rate: 1 KHz – 5 Hz
6 layer of detector=6*(Si wafer+4ASIC+DIF)
3. 1 GeV e- hit with 6 layer of detector: between the layers
and in front of 1st layer W plate placed.
All the run was same: 3600 sec.
4. Example of MIP for one chip, channel,column
Pedestal
1st MIP
2nd MIP
16. Summary:
Hit distribution for different radiation length analysed.
The size of shower estimated for different radiation length.
It seems beam not aligned proper or we had a shower leakage
due to particle loose, which gives the discrepancy in end of X0 and beginning of
3X0 configuration (same for 3X0 and 6X0).
Need to verify it with same geometry with simulation!